Low Power State Retention solution for i.MX91 SoCs

domasgim — Mon, 30 Mar 2026 04:51:46 GMT

Hello,

I am following up on a previous discussion regarding GPIO output state retention during suspend mode on i.MX91:

https://community.nxp.com/t5/i-MX-Processors/Preserve-GPIO-output-state-inside-suspend-mode-in-i-MX91/m-p/2339310/highlight/true#M244633

From that thread, it was confirmed that i.MX91 does not support GPIO state retention in low-power modes due to pad power domain behavior.

We are currently working with a board based on i.MX91 where several peripherals (e.g., LEDs and isolated outputs) depend on GPIO output states, and we need to preserve those states during suspend-to-RAM.

Since native retention is not available, we are evaluating external solutions (e.g., latches or shift registers powered from an always-on rail). Before proceeding with hardware changes, we would like to ask:

Are there any recommended approaches to maintain GPIO output state during suspend on i.MX91 (either hardware or software-assisted)?
Is it possible to keep specific GPIO banks or pad domains powered during suspend to avoid losing output state?
Are there any low-power modes where GPIO output drivers remain active?
Are there any reference designs, application notes, or best practices for handling this type of requirement on i.MX91?

Any guidance would be greatly appreciated as we are still in the design phase and evaluating possible solutions.

Kind regards,

Re: Low Power State Retention solution for i.MX91 SoCs

Zhiming_Liu — Tue, 31 Mar 2026 01:56:40 GMT

Hi,

Are there any recommended approaches to maintain GPIO output state during suspend on i.MX91 (either hardware or software-assisted)?

-->You can choose an external D-type latch or a buffer with a hold function, such as the 74HC/HCT373, 74HC595, or SN74LVC1G373. Furthermore, this latch must be powered by the AON(Always On) power domain(NVCC_AON). AON domain will not lose power when suspended.

Is it possible to keep specific GPIO banks or pad domains powered during suspend to avoid losing output state?

-->The NVCC_GPIO is not closed during suspend, but the internal PAD driver is closed. I checked the GPC registers and found that there are no dedicated bits for the GPIOs, so it is not possible to prevent the PAD driver from being powered down by modifying the GPC logic.

Are there any low-power modes where GPIO output drivers remain active?

-->The i.MX91 does not have a pad retention mechanism similar to that of the i.MX8ULP's FSGPIO/HSGPIO.

Are there any reference designs, application notes, or best practices for handling this type of requirement on i.MX91?

-->Currently, NXP does not offer a similar reference design, but implementing an external latch should not be too difficult.

Best Regards,
Zhiming

topic Low Power State Retention solution for i.MX91 SoCs in i.MX Processors

Low Power State Retention solution for i.MX91 SoCs

Re: Low Power State Retention solution for i.MX91 SoCs