<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックRe: IMX93 UART 3 &amp;amp; UART 4 Have same pin resource</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX93-UART-3-amp-UART-4-Have-same-pin-resource/m-p/2341853#M244682</link>
    <description>&lt;P&gt;If RD0 and TD0 of enet1 are not needed for other functions, then lpuart3 can route to these two pins. In this case, lpuart4 can route to gpio io15 and io14.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="1.png" style="width: 488px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/380756i16FCD699C13FCA69/image-size/large?v=v2&amp;amp;px=999" role="button" title="1.png" alt="1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;If RD0 and TD0 of enet2 are not needed for other functions, then lpuart4 can route to these two pins. In this case, lpuart3 can route to gpio io15 and io14.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="2.png" style="width: 490px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/380757i983D81EEE5C38709/image-size/large?v=v2&amp;amp;px=999" role="button" title="2.png" alt="2.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Sun, 29 Mar 2026 22:36:59 GMT</pubDate>
    <dc:creator>vopal</dc:creator>
    <dc:date>2026-03-29T22:36:59Z</dc:date>
    <item>
      <title>IMX93 UART 3 &amp; UART 4 Have same pin resource</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX93-UART-3-amp-UART-4-Have-same-pin-resource/m-p/2339860#M244648</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;We are planning to use UART on the i.MX93 module. According to the datasheet, there are 8 LPUART instances available. However, we noticed that LPUART3 and LPUART4 appear to share the same pin resources:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;GPIO_IO15&lt;/LI&gt;&lt;LI&gt;GPIO_IO14&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;We would like to understand how it is possible to use both LPUART3 and LPUART4 if they are mapped to the same pins. Additionally, what is the reason behind both UART instances sharing the same pin resources?&lt;/P&gt;&lt;P&gt;We also observed this configuration in the pinmux header file and would appreciate further clarification.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;BR /&gt;#define MX93_PAD_GPIO_IO15__GPIO2_IO15 0x004C 0x01FC 0x0000 0x0 0x0&lt;BR /&gt;#define &lt;STRONG&gt;MX93_PAD_GPIO_IO15__LPUART3_RX&lt;/STRONG&gt; 0x004C 0x01FC 0x0418 0x1 0x0&lt;BR /&gt;#define MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07 0x004C 0x01FC 0x0000 0x2 0x0&lt;BR /&gt;#define MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x004C 0x01FC 0x0000 0x3 0x0&lt;BR /&gt;#define MX93_PAD_GPIO_IO15__LPSPI8_SCK 0x004C 0x01FC 0x0000 0x4 0x0&lt;BR /&gt;#define MX93_PAD_GPIO_IO15__LPUART8_RTS_B 0x004C 0x01FC 0x0000 0x5 0x0&lt;BR /&gt;#define &lt;STRONG&gt;MX93_PAD_GPIO_IO15__LPUART4_RX&lt;/STRONG&gt; 0x004C 0x01FC 0x0424 0x6 0x0&lt;BR /&gt;#define MX93_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x004C 0x01FC 0x03A4 0x7 0x0&lt;BR /&gt;&lt;BR /&gt;Thanks&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 26 Mar 2026 08:01:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX93-UART-3-amp-UART-4-Have-same-pin-resource/m-p/2339860#M244648</guid>
      <dc:creator>deepakraj</dc:creator>
      <dc:date>2026-03-26T08:01:42Z</dc:date>
    </item>
    <item>
      <title>Re: IMX93 UART 3 &amp; UART 4 Have same pin resource</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX93-UART-3-amp-UART-4-Have-same-pin-resource/m-p/2340238#M244652</link>
      <description>&lt;P&gt;You need to select according to MUX Mode Select Field. You may use either UART3 or UART4&lt;/P&gt;&lt;P&gt;110 - Select mux mode: ALT6 mux port: LPUART4_TX of instance: lpuart4&lt;/P&gt;&lt;P&gt;001 - Select mux mode: ALT1 mux port: LPUART3_TX of instance: lpuart3&lt;/P&gt;</description>
      <pubDate>Thu, 26 Mar 2026 10:59:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX93-UART-3-amp-UART-4-Have-same-pin-resource/m-p/2340238#M244652</guid>
      <dc:creator>db16122</dc:creator>
      <dc:date>2026-03-26T10:59:13Z</dc:date>
    </item>
    <item>
      <title>Re: IMX93 UART 3 &amp; UART 4 Have same pin resource</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX93-UART-3-amp-UART-4-Have-same-pin-resource/m-p/2340728#M244670</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/207815"&gt;@db16122&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;P&gt;So, it’s not possible to use UART3 and UART4 at the same time, right?&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;Thanks&lt;/DIV&gt;</description>
      <pubDate>Fri, 27 Mar 2026 04:38:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX93-UART-3-amp-UART-4-Have-same-pin-resource/m-p/2340728#M244670</guid>
      <dc:creator>deepakraj</dc:creator>
      <dc:date>2026-03-27T04:38:14Z</dc:date>
    </item>
    <item>
      <title>Re: IMX93 UART 3 &amp; UART 4 Have same pin resource</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX93-UART-3-amp-UART-4-Have-same-pin-resource/m-p/2341264#M244672</link>
      <description>&lt;P&gt;You may use UART3 and UART4 at same time but with different port setting. You can not use 2 UART with 2pin rxtx. You can use 2 uart with 4pin rx1tx1 rx2tx2&lt;/P&gt;&lt;P&gt;For detailed pin setting you need to refer to IMX93 usermanual&lt;/P&gt;</description>
      <pubDate>Fri, 27 Mar 2026 13:23:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX93-UART-3-amp-UART-4-Have-same-pin-resource/m-p/2341264#M244672</guid>
      <dc:creator>db16122</dc:creator>
      <dc:date>2026-03-27T13:23:56Z</dc:date>
    </item>
    <item>
      <title>Re: IMX93 UART 3 &amp; UART 4 Have same pin resource</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX93-UART-3-amp-UART-4-Have-same-pin-resource/m-p/2341853#M244682</link>
      <description>&lt;P&gt;If RD0 and TD0 of enet1 are not needed for other functions, then lpuart3 can route to these two pins. In this case, lpuart4 can route to gpio io15 and io14.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="1.png" style="width: 488px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/380756i16FCD699C13FCA69/image-size/large?v=v2&amp;amp;px=999" role="button" title="1.png" alt="1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;If RD0 and TD0 of enet2 are not needed for other functions, then lpuart4 can route to these two pins. In this case, lpuart3 can route to gpio io15 and io14.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="2.png" style="width: 490px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/380757i983D81EEE5C38709/image-size/large?v=v2&amp;amp;px=999" role="button" title="2.png" alt="2.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sun, 29 Mar 2026 22:36:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX93-UART-3-amp-UART-4-Have-same-pin-resource/m-p/2341853#M244682</guid>
      <dc:creator>vopal</dc:creator>
      <dc:date>2026-03-29T22:36:59Z</dc:date>
    </item>
  </channel>
</rss>

