topic Re: SAIF1 as output in i.MX Processors

SAIF1 as output

carlosrivera — Mon, 24 Feb 2014 21:30:12 GMT

Hello

I am using WinCE 6.3 on a custom board based on i.mx28EVK, and I need to reconfigure the audio ports in order to play a sound.

On i.mx28 EVK SAIF0 is configured as output while SAIF1 is configured as input; to have full duplex interface. I tried to use the same configuration as SAIF0 on SAIF1 and remove SAIF0 from the driver, but the program hangs when I try un a *.wav file.

// Init SAIF0(AUDIOOUT)

// Reset SAIF0

HW_SAIF_CTRL_SET(0, BM_SAIF_CTRL_SFTRST);

// Wait for some time

HW_SAIF_CTRL_RD(0);

// In order to configure SAIF0, we must first clear the CLKGATE and SFTRST bit

HW_SAIF_CTRL_CLR(0, BM_SAIF_CTRL_SFTRST);

// Wait for some time

HW_SAIF_CTRL_RD(0);

// Clear the clock gate for normal operation

HW_SAIF_CTRL_CLR(0, BM_SAIF_CTRL_CLKGATE);

// Wait for some time

HW_SAIF_CTRL_RD(0);

// 16bit sample

HW_SAIF_CTRL_WR(0, BF_SAIF_CTRL_SFTRST(0) |

BF_SAIF_CTRL_CLKGATE(0) |

BF_SAIF_CTRL_BITCLK_MULT_RATE(0) |

BF_SAIF_CTRL_BITCLK_BASE_RATE(0) |

BF_SAIF_CTRL_FIFO_ERROR_IRQ_EN(0) |

BF_SAIF_CTRL_FIFO_SERVICE_IRQ_EN(0) |

BF_SAIF_CTRL_DMAWAIT_COUNT(0) |

BF_SAIF_CTRL_CHANNEL_NUM_SELECT(0) |

BF_SAIF_CTRL_BIT_ORDER(0) |

BF_SAIF_CTRL_DELAY(1) |

BF_SAIF_CTRL_JUSTIFY(0) |

BF_SAIF_CTRL_LRCLK_POLARITY(0) |

BF_SAIF_CTRL_BITCLK_EDGE(0) |

BF_SAIF_CTRL_WORD_LENGTH(0) |

BF_SAIF_CTRL_BITCLK_48XFS_ENABLE(0) |

BF_SAIF_CTRL_SLAVE_MODE(0) |

BF_SAIF_CTRL_READ_MODE(0) |

BF_SAIF_CTRL_RUN(1));

The configuration code I am trying to modify is located in bsphwctxt.cpp.

Is there ant other place where I should modify the code?.

I will appreciate any help.

Carlos

Re: SAIF1 as output

Bio_TICFSL — Tue, 11 Mar 2014 15:56:11 GMT

I was able to reproduced the issue on Wince 6.0 bsp, AdeneoEmbedded team have you any suggestion for this issue? have you seen this on wince 7]

I just checked the initialization sequence, and this procedure works as workaround for me, however I used full duplex on both SAIF:

- Clear SFTRST and CLKGATE in HW_SAIF_CTRL.

- Configure HW_SAIF_CTRL for the required frame format.

- Fill the FIFO with the first 4 sample pairs (for stereo) from your data stream by writing to HW_SAIF_DATA.

- Set up your interrupt handler for IRQ #10 (SAIF1&2 FIFO IRQ).

- Clear FIFO_UNDERFLOW_IRQ and FIFO_OVERFLOW_IRQ in HW_SAIF_STAT by writing a 1 to those bits of HW_SAIF_STAT_CLR (the SCT clear variant).

- Set FIFO_SERVICE_IRQ_EN and FIFO_ERROR_IRQ_EN in HW_SAIF_CTRL to 1.

- Enable IRQ #10 in the ICOLL.

- Set HW_SAIF_CTRL.B.RUN to start transmitting.

When you get an interrupt on IRQ #10:

- Check the HW_SAIF_STAT.B.FIFO_UNDERFLOW_IRQ and HW_SAIF_STAT.B.FIFO_OVERFLOW_IRQ bits to see if there was a FIFO error. If so, clear the appropriate IRQ and take whatever action you need.

- If HW_SAIF_STAT.B.FIFO_SERVICE_IRQ is set, fill the FIFO again by writing sample frames to HW_SAIF_DATA. For each frame, that will be one write for each pair of channels, as described in the RM. You can watch for HW_SAIF_STAT.B.FIFO_SERVICE_IRQ to clear to know when the FIFO has been filled.

Also checked the Linux BSP and it works well on it, I checked mxs-dai.c, mxs_saif_0 and mxs_saif_1 need to be changed as belows:

struct mxs_pcm_dma_params mxs_saif_0 = {

.name = "mxs-saif-0",

.dma_ch = MXS_DMA_CHANNEL_AHB_APBX_SAIF1

.irq = IRQ_SAIF1_DMA

};

struct mxs_pcm_dma_params mxs_saif_1 = {

.name = "mxs-saif-1",

.dma_ch = MXS_DMA_CHANNEL_AHB_APBX_SAIF2

.irq = IRQ_SAIF2_DMA

};

hope this helps

Regards

Re: SAIF1 as output

YixingKong — Thu, 10 Apr 2014 07:00:17 GMT

Carlos

Had your issue got resolved? If yes, we are going to close the discussion in 3 days. If you still need help, please feel free to reply with an update to this discussion.

Thanks,

Yixing

Re: SAIF1 as output

YixingKong — Tue, 15 Apr 2014 07:17:49 GMT

Carlos

This discussion is closed since no activity. If you still need help, please feel free to reply with an update to this discussion, or create another discussion.

Thanks,

Yixing