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    <title>topic Re: FlexSPI IP Command Read Transfer Size Limit in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/FlexSPI-IP-Command-Read-Transfer-Size-Limit/m-p/2339968#M244650</link>
    <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/261016"&gt;@kvsh&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;Thanks for your interest in NXP MIMXRT series!&lt;/P&gt;
&lt;P&gt;128 bytes is only the capacity of the IP RX FIFO; it is not the total transfer limit for the IP command read. Please refer to `evkmimxrt1170_flexspi_nor_edma_transfer_cm7` in the RT1170-EVK SDK. Thanks!&lt;/P&gt;
&lt;P&gt;Best regards,&lt;BR /&gt;Gavin&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Thu, 26 Mar 2026 09:31:33 GMT</pubDate>
    <dc:creator>Gavin_Jia</dc:creator>
    <dc:date>2026-03-26T09:31:33Z</dc:date>
    <item>
      <title>FlexSPI IP Command Read Transfer Size Limit</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/FlexSPI-IP-Command-Read-Transfer-Size-Limit/m-p/2339359#M244636</link>
      <description>&lt;DIV&gt;I am reading 256 bytes using a FlexSPI IP command DMA read on an RT1050 custom board. The first 128 bytes are correct, but the second 128 bytes repeat the first 128 bytes. Is it correct that it is not possible to read more than the RX FIFO size in one IP command read transfer, and that I need to use an AHB read instead?&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;Code is below.&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;AT_NONCACHEABLE_SECTION_ALIGN(&lt;/SPAN&gt;&lt;SPAN&gt;uint32_t&lt;/SPAN&gt;&lt;SPAN&gt; destAddr[256], 8);&lt;/SPAN&gt;&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;edma_handle_t&lt;/SPAN&gt;&lt;SPAN&gt; txEdmaHandle, rxEdmaHandle;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;flexspi_edma_handle_t&lt;/SPAN&gt;&lt;SPAN&gt; flexspiEdmaHandle;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;#define&lt;/SPAN&gt;&lt;SPAN&gt; FLEXSPI_DMA_TX_CHANNEL 1&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;#define&lt;/SPAN&gt;&lt;SPAN&gt; FLEXSPI_DMA_RX_CHANNEL 0&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;#define NUM_BYTES_RX 256&lt;/SPAN&gt;&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;P&gt;&lt;SPAN&gt;edma_config_t&lt;/SPAN&gt;&lt;SPAN&gt; userConfig;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;DMAMUX_Init(EXAMPLE_DMAMUX);&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;DMAMUX_EnableAlwaysOn(EXAMPLE_DMAMUX, 0, true);&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;DMAMUX_EnableChannel(EXAMPLE_DMAMUX, 0);&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;EDMA_GetDefaultConfig(&amp;amp;userConfig);&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;EDMA_Init(EXAMPLE_DMA, &amp;amp;userConfig);&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;EDMA_CreateHandle(&amp;amp;rxEdmaHandle, EXAMPLE_DMA, FLEXSPI_DMA_RX_CHANNEL);&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;EDMA_CreateHandle(&amp;amp;txEdmaHandle, EXAMPLE_DMA, FLEXSPI_DMA_TX_CHANNEL);&lt;/SPAN&gt;&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;P&gt;&lt;SPAN&gt;FLEXSPI_TransferCreateHandleEDMA(EXAMPLE_FLEXSPI,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;amp;flexspiEdmaHandle,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;EDMA_Callback,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;NULL,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;amp;txEdmaHandle,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;amp;rxEdmaHandle);&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;// tried different sizes, no success&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;flexspiEdmaHandle.&lt;/SPAN&gt;&lt;SPAN&gt;nsize&lt;/SPAN&gt;&lt;SPAN&gt; = &lt;/SPAN&gt;&lt;SPAN&gt;kFLEXPSI_EDMAnSize8Bytes&lt;/SPAN&gt;&lt;SPAN&gt;; &lt;/SPAN&gt;&lt;SPAN&gt;//kFLEXPSI_EDMAnSize1Bytes;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;flexspi_transfer_t&lt;/SPAN&gt;&lt;SPAN&gt; xfer = {&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;.port = FLASH_PORT,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;.cmdType = &lt;/SPAN&gt;&lt;SPAN&gt;kFLEXSPI_Read&lt;/SPAN&gt;&lt;SPAN&gt;, &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;.seqIndex = 0,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;.SeqNumber = 1,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;.deviceAddress= 0,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;.data = destAddr,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;.dataSize = NUM_BYTES_RX&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;};&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;status_t&lt;/SPAN&gt;&lt;SPAN&gt; st = FLEXSPI_TransferEDMA(EXAMPLE_FLEXSPI, &amp;amp;flexspiEdmaHandle, &amp;amp;xfer);&lt;/SPAN&gt;&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Wed, 25 Mar 2026 12:53:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/FlexSPI-IP-Command-Read-Transfer-Size-Limit/m-p/2339359#M244636</guid>
      <dc:creator>kvsh</dc:creator>
      <dc:date>2026-03-25T12:53:35Z</dc:date>
    </item>
    <item>
      <title>Re: FlexSPI IP Command Read Transfer Size Limit</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/FlexSPI-IP-Command-Read-Transfer-Size-Limit/m-p/2339968#M244650</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/261016"&gt;@kvsh&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;Thanks for your interest in NXP MIMXRT series!&lt;/P&gt;
&lt;P&gt;128 bytes is only the capacity of the IP RX FIFO; it is not the total transfer limit for the IP command read. Please refer to `evkmimxrt1170_flexspi_nor_edma_transfer_cm7` in the RT1170-EVK SDK. Thanks!&lt;/P&gt;
&lt;P&gt;Best regards,&lt;BR /&gt;Gavin&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 26 Mar 2026 09:31:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/FlexSPI-IP-Command-Read-Transfer-Size-Limit/m-p/2339968#M244650</guid>
      <dc:creator>Gavin_Jia</dc:creator>
      <dc:date>2026-03-26T09:31:33Z</dc:date>
    </item>
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