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    <title>i.MX Processorsのトピックi.MX95 EVK (19x19): CAN1 on M7 core not working</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX95-EVK-19x19-CAN1-on-M7-core-not-working/m-p/2337302#M244594</link>
    <description>&lt;P&gt;I am trying to use &lt;STRONG&gt;CAN1 on the M7 core&lt;/STRONG&gt; of the &lt;STRONG&gt;i.MX95 19x19 EVK&lt;/STRONG&gt; to receive/transmit CAN messages.&amp;nbsp;&lt;/P&gt;&lt;P&gt;I am using the i.MX95 EVK (19x19) with the M7 core, while Yocto Linux runs on the A-core with&amp;nbsp;&lt;STRONG&gt;SW9:3 set to ON&lt;/STRONG&gt; for CAN routing.&lt;/P&gt;&lt;P&gt;I used the FlexCAN SDK example on the M7 core. Through the system manager I&amp;nbsp;granted M7 access to these pins using '&lt;STRONG&gt;mm 0x443c01e0 0x6&lt;/STRONG&gt;' and '&lt;STRONG&gt;mm 0x443c01e4 0x6&lt;/STRONG&gt;', but it still does not work.&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;How should FlexCAN1 be properly enabled on the M7 core for i.MX95? Are&amp;nbsp;there any additional configurations required?&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Mon, 23 Mar 2026 05:11:27 GMT</pubDate>
    <dc:creator>sarvesh_n</dc:creator>
    <dc:date>2026-03-23T05:11:27Z</dc:date>
    <item>
      <title>i.MX95 EVK (19x19): CAN1 on M7 core not working</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX95-EVK-19x19-CAN1-on-M7-core-not-working/m-p/2337302#M244594</link>
      <description>&lt;P&gt;I am trying to use &lt;STRONG&gt;CAN1 on the M7 core&lt;/STRONG&gt; of the &lt;STRONG&gt;i.MX95 19x19 EVK&lt;/STRONG&gt; to receive/transmit CAN messages.&amp;nbsp;&lt;/P&gt;&lt;P&gt;I am using the i.MX95 EVK (19x19) with the M7 core, while Yocto Linux runs on the A-core with&amp;nbsp;&lt;STRONG&gt;SW9:3 set to ON&lt;/STRONG&gt; for CAN routing.&lt;/P&gt;&lt;P&gt;I used the FlexCAN SDK example on the M7 core. Through the system manager I&amp;nbsp;granted M7 access to these pins using '&lt;STRONG&gt;mm 0x443c01e0 0x6&lt;/STRONG&gt;' and '&lt;STRONG&gt;mm 0x443c01e4 0x6&lt;/STRONG&gt;', but it still does not work.&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;How should FlexCAN1 be properly enabled on the M7 core for i.MX95? Are&amp;nbsp;there any additional configurations required?&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 23 Mar 2026 05:11:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX95-EVK-19x19-CAN1-on-M7-core-not-working/m-p/2337302#M244594</guid>
      <dc:creator>sarvesh_n</dc:creator>
      <dc:date>2026-03-23T05:11:27Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX95 EVK (19x19): CAN1 on M7 core not working</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX95-EVK-19x19-CAN1-on-M7-core-not-working/m-p/2338092#M244615</link>
      <description>&lt;P&gt;&lt;STRONG&gt;Ensure the M7 really owns the FlexCAN1 peripheral&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;On i.MX95, &lt;STRONG&gt;every peripheral is owned by SCMI/System Manager by default&lt;/STRONG&gt;.&lt;BR /&gt;You must explicitly grant ownership of:&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;FlexCAN1 Registers&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;PER: CAN1 (AIPSTZ / peripheral ID)&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;FlexCAN1 Message RAM&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;CAN1_MR (separate peripheral range)&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;CAN1 I/O pads&lt;/STRONG&gt;&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;GPIO_IOxx pins corresponding to &lt;STRONG&gt;CAN1_TX&lt;/STRONG&gt; and &lt;STRONG&gt;CAN1_RX&lt;/STRONG&gt;&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;Your commands:&lt;/P&gt;
&lt;P&gt;mm 0x443c01e0 0x6&lt;/P&gt;
&lt;P&gt;mm 0x443c01e4 0x6&lt;/P&gt;
&lt;P&gt;only modify the &lt;EM&gt;pin mode&lt;/EM&gt;—they &lt;STRONG&gt;do not&lt;/STRONG&gt; grant the M7 &lt;EM&gt;permissions&lt;/EM&gt;.&lt;/P&gt;
&lt;P&gt;You must request ownership via SCFW (System Controller Firmware).&lt;/P&gt;
&lt;P&gt;In Cortex‑M7 SDK examples, this is done via:&amp;nbsp;&lt;/P&gt;
&lt;P&gt;sc_err_t err;&lt;/P&gt;
&lt;P&gt;err = sc_rm_get_partition(&amp;amp;ptn);&lt;/P&gt;
&lt;P&gt;err = sc_rm_assign_resource(ptn, SC_R_CAN_1);&lt;/P&gt;
&lt;P&gt;err = sc_rm_assign_resource(ptn, SC_R_CAN_1_MEM);&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Show more lines&lt;/P&gt;
&lt;P&gt;If this step is missing, CAN1 registers appear to “work” but &lt;STRONG&gt;nothing actually happens&lt;/STRONG&gt;.&lt;/P&gt;</description>
      <pubDate>Tue, 24 Mar 2026 04:21:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX95-EVK-19x19-CAN1-on-M7-core-not-working/m-p/2338092#M244615</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2026-03-24T04:21:21Z</dc:date>
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