topic Re: FEC controller TDAR bit not cleared (Uboot) in i.MX Processors

FEC controller TDAR bit not cleared (Uboot)

Decastro — Tue, 27 Jan 2026 15:21:44 GMT

Hi togehter,

I encountered an issue when enabling the KSZ9893 switch in U-Boot (IMX6dl). After a cold reset and entering U-Boot, the TDAR bit is never cleared by the FEC after it has been set to “1” to indicate that there is data to be transmitted.

However, if the system first boots into Linux and then re-enters U-Boot via a warm reset (using reboot), the issue does not occur.

I compared all FEC and KSZ9893 registers between cold reset and warm reset scenarios and found them to be identical. I also compared the clock and PLL configurations in both cases (including ANALOG_PLL_528, ANALOG_PFD_528, CBCMR, CBCD R, and CCGR1), and they are exactly the same.

Is it possible that some initialization or configuration step performed during the warm reset path is missing during the cold reset, which could result in the TDAR bit not being cleared in the cold reset case?

Thanks a lot in advance

Re: FEC controller TDAR bit not cleared (Uboot)

pengyong_zhang — Tue, 03 Mar 2026 02:00:02 GMT

Hi @Decastro

Working on your problem and will give you the feedback ASAP.

Which version of the BSP code are you using?

B.R

Re: FEC controller TDAR bit not cleared (Uboot)

Decastro — Tue, 21 Apr 2026 07:47:45 GMT

Hi,
the BSP i am using is 6.12-walnascar, Distro fsl-imx-xwayland, uboot version lf_v2025.04.

thank you for the response.

Re: FEC controller TDAR bit not cleared (Uboot)

Decastro — Wed, 22 Apr 2026 06:35:03 GMT

I finally figured out that there were two problems I needed to fix: 1. RGMII uses GPIO_16 (RGMII_TX_CTL) as a clock source, so I had to configure it in the device tree (DT). 2. IOMUXC_GPR1 was not configured in mx6dlsabresd.c.
The problem is now solved. Thank you for your help and the issue can be closed