topic Re: How to Configure a PCIe FPGA Endpoint for the i.MX8MP in i.MX Processors

How to Configure a PCIe FPGA Endpoint for the i.MX8MP

NXP_USER_05 — Tue, 17 Feb 2026 18:55:10 GMT

Hi ,

I am working with the PCIe Root Complex on the i.MX8MP and a custom FPGA(Artix 7) configured as a PCIe endpoint. The PCIe link comes up successfully and the endpoint is enumerated during boot. Below is the relevant boot log:

2.500513] imx6q-pcie 33800000.pcie: host bridge /soc@0/pcie@33800000 ranges:
[ 2.507832] imx6q-pcie 33800000.pcie: IO 0x001ff80000..0x001ff8ffff -> 0x0000000000
[ 2.508459] pps pps0: new PPS source ptp0
[ 2.516088] imx6q-pcie 33800000.pcie: MEM 0x0018000000..0x001fefffff -> 0x0018000000
[ 2.529393] fec 30be0000.ethernet: Invalid MAC address: 00:00:00:00:00:00
[ 2.536303] fec 30be0000.ethernet: Using random MAC address: 4e:ba:b3:4a:a3:b9
[ 2.745496] imx6q-pcie 33800000.pcie: iATU: unroll T, 4 ob, 4 ib, align 64K, limit 16G
[ 2.853903] imx6q-pcie 33800000.pcie: PCIe Gen.1 x1 link up
[ 2.859611] imx6q-pcie 33800000.pcie: PCIe Gen.1 x1 link up
[ 2.865214] imx6q-pcie 33800000.pcie: Link up, Gen1
[ 2.870114] imx6q-pcie 33800000.pcie: PCIe Gen.1 x1 link up
[ 2.875881] imx6q-pcie 33800000.pcie: PCI host bridge to bus 0000:00
[ 2.882281] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 2.887795] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
[ 2.893995] pci_bus 0000:00: root bus resource [mem 0x18000000-0x1fefffff]
[ 2.900922] pci 0000:00:00.0: [16c3:abcd] type 01 class 0x060400
[ 2.906964] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x000fffff]
[ 2.913262] pci 0000:00:00.0: reg 0x38: [mem 0x00000000-0x0000ffff pref]
[ 2.920046] pci 0000:00:00.0: supports D1
[ 2.924084] pci 0000:00:00.0: PME# supported from D0 D1 D3hot D3cold
[ 2.933735] pci 0000:01:00.0: [10ee:7011] type 00 class 0x060000
[ 2.939854] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x00007fff]
[ 2.946320] pci 0000:01:00.0: enabling Extended Tags
[ 2.961365] pci 0000:00:00.0: BAR 0: assigned [mem 0x18000000-0x180fffff]
[ 2.968226] pci 0000:00:00.0: BAR 14: assigned [mem 0x18100000-0x181fffff]
[ 2.975141] pci 0000:00:00.0: BAR 6: assigned [mem 0x18200000-0x1820ffff pref]
[ 2.982396] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
[ 2.987647] pci 0000:00:00.0: bridge window [mem 0x18100000-0x181fffff]
[ 2.994923] pcieport 0000:00:00.0: PME: Signaling with IRQ 221

The PCIe endpoint (Vendor ID 10ee, Device ID 7011) is detected correctly, and BAR0 is reported with a size of 16 KB.

However, when loading a custom out-of-tree PCIe driver, the probe fails with the following error:

[ 9.517480] pcie_example: loading out-of-tree module taints kernel.
[ 9.533840] pcie_example: probing 10ee:7011
[ 9.539507] pcie_example 0000:01:00.0: can't enable device:
BAR 0 [mem 0x00000000-0x00007fff] not claimed
[ 9.567806] pcie_example: pci_enable_device failed

It appears that BAR0 is not being assigned a system memory address, causing pci_enable_device() to fail in the driver.

Also attached the dts file for your refrence.

Could you please advise:

Why the endpoint BAR is not being claimed/assigned by the i.MX8MP PCIe Root Complex?
Whether any specific device tree, kernel configuration, or PCIe controller settings are required to ensure proper BAR allocation for PCIe endpoints on i.MX8MP?

Any guidance would be greatly appreciated.

Thank you.

Re: How to Configure a PCIe FPGA Endpoint for the i.MX8MP

Oswalag — Thu, 19 Feb 2026 19:40:06 GMT

Hello,

The issue seems to be caused by the class code of the EP.

Your FPGA endpoint is currently reporting a PCI Class Code of 0x060000, which identifies the device as a Host Bridge. This classification is not valid for a Type‑0 PCIe endpoint function. Because the Linux PCI subsystem interprets the device as a bridge rather than a standard endpoint, it does not assign or claim BAR resources for it. As a result, the call to pci_enable_device() fails with the message “BAR 0 not claimed.”, please take a look on the link below:

https://stackoverflow.com/questions/46476844/pci-enable-device-fails-after-remove-rescan

Also, please refer to the below U-boot source code from NXP for the supported PCI drivers.

uboot-imx/drivers /pci/

Re: How to Configure a PCIe FPGA Endpoint for the i.MX8MP

NXP_USER_05 — Wed, 25 Feb 2026 08:24:20 GMT

After changing the PCIe Endpoint class code from 0x060000 to 0x058000, the device is successfully enabled and the PCIe link comes up correctly.

Now I am trying to write data from the Root Complex (RC) to the Endpoint (EP) using PIO / MMIO access.
Write Operation from RC

I am using devmem2 on the RC side:

$ devmem2 0x18100004 w 0xDEADBEEF

Output:
/dev/mem opened.
Memory mapped at address 0xffff84e9b000.
Read at address 0x18100004 (0xffff84e9b004): 0xFFFFFFFF
Write at address 0x18100004 (0xffff84e9b004): 0xDEADBEEF, readback 0xDEADBEEF

Observation on EP Side

Using ILA in Vivado, I can see the AXI write data (WDATA = 0xDEADBEEF) reaching the PCIe IP.

However, when I try to read the data from the EP register logic, I only get dummy values (0xFFFFFFFF).

Additionally:

A register shows the value 0xDEC0DE1C

RVALID remains 0

Read response never completes

Questions

1. Is additional configuration required on the EP side to properly handle PIO/MMIO writes?

2.Could this be related to BAR configuration, address decoding, or AXI slave response handling?

Thanks in advance for your support.