i.MX ProcessorsのトピックRe: Simultan access GPIO13 from core m7 and GPIO9 from core m4

Simultan access GPIO13 from core m7 and GPIO9 from core m4

AndreasL — Thu, 08 Jan 2026 09:54:21 GMT

Dear NXP team,

CPU i.mxrt1176CVM8A.

In my application I have on core m4 motor control application and on core m7 real time application.

If I access simultaneously from core m7 GPIO13 and from core m4 GPIO9, the access to GPIO9 will be delayed more than 31µs.

In the datasheet I can found chapter 13.1 And in chapter 2.1.2 System Bus Diagram following information

When LPSRMIX master is accessing GPIO13, XB will hold WAKEUPMIX master requests to any AIPS4 peripheral until current LPSRMIX master access is completed. Because GPIO13 access is based on 32 K clock as it’s in SNVS domain to save power, these WAKEUPMIX master requests could be held for over 31µs.

I understand the delay from core m7 between AIPS4 to GPIO13(LPSRMIX-Domin) but not the delay from more than 31µs to the GPIO9(WAKEUPMIX) pin GPIO_AD_31 over the direct way from core m4 to GPIO-SOC.

Please find in the attachment the bus diagram, I have marked with green and blue communications:

Please can you help me. I have with this delay a problem with the motor control cycle!

Re: Simultan access GPIO13 from core m7 and GPIO9 from core m4

Pablo_Ramos — Thu, 08 Jan 2026 18:09:18 GMT

Hi @AndreasL,

I am not able to see the attachment of the bus diagram. Could you please send it again?

What are the configurations of the Cortex?

What are the speeds of both Cortex?

Best Regards,
Pablo

Re: Simultan access GPIO13 from core m7 and GPIO9 from core m4

AndreasL — Fri, 09 Jan 2026 07:10:12 GMT

Hi Pablo,

Many thanks for your quick response.

The cortex m7 is the master the main clock is: 792.000.000 Hz
The main clock of the cortex m4 is: 392.727.258 Hz
Bus clock root is: 240 MHz
Bus LPSR clock root is: 160 MHz

Please find also attached the configuration files.

Best Regards,
Andreas

Re: Simultan access GPIO13 from core m7 and GPIO9 from core m4

Pablo_Ramos — Fri, 09 Jan 2026 18:57:43 GMT

Hi @AndreasL,

Thanks for the information.

During the period when GPIO13 registers are being accessed, the LPSR domain bus will be on hold.

In this case, GPIO9 is part of the LPSR domain, which means that communication from the M4 core to GPIO9 must wait until the M7 core finishes accessing the GPIO13 registers.

See Table 3: i.MX RT1170 Modules List in the i.MX RT1170 Crossover Processors Data Sheet.

If the motor control cycle implementation is being affected by this behavior, you could try using a GPIO other than GPIO13.

Best Regards,

Pablo