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    <title>topic Re: iMX7D 16-bit DDR3 Implementation Issue in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX7D-16-bit-DDR3-Implementation-Issue/m-p/2253319#M242576</link>
    <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;i.MX7D supports&amp;nbsp;16/32-bit DDR3L/LPDDR2/LPDDR3-1066 memories.&lt;/P&gt;
&lt;P&gt;You can configure this directly in RPA when doing the DDR stress test.&lt;/P&gt;
&lt;P&gt;Best regards.&lt;/P&gt;</description>
    <pubDate>Tue, 02 Dec 2025 15:34:48 GMT</pubDate>
    <dc:creator>JorgeCas</dc:creator>
    <dc:date>2025-12-02T15:34:48Z</dc:date>
    <item>
      <title>iMX7D 16-bit DDR3 Implementation Issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX7D-16-bit-DDR3-Implementation-Issue/m-p/2252909#M242553</link>
      <description>&lt;P&gt;Hi, NXP team&lt;/P&gt;&lt;P&gt;Does iMX7D support 16-bit DDR3 implementation? In RM DDRC_MSTR[13:12] = DATA_BUS_WIDTH = 2'b01: Half DQ bus width to SDRAM-DRAM_DATA[15:0], it seems that DDRC can work with 16-bit DDR3 chip, but it doesn't work with my test. I just want to make sure if iMX7D DDRC can work with 16-bit DDR3 or not, otherwise something wrong in my test.&lt;/P&gt;&lt;P&gt;Thanks!&lt;/P&gt;&lt;P&gt;Cheng Shi&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 02 Dec 2025 07:47:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX7D-16-bit-DDR3-Implementation-Issue/m-p/2252909#M242553</guid>
      <dc:creator>x10</dc:creator>
      <dc:date>2025-12-02T07:47:12Z</dc:date>
    </item>
    <item>
      <title>Re: iMX7D 16-bit DDR3 Implementation Issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX7D-16-bit-DDR3-Implementation-Issue/m-p/2253319#M242576</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;i.MX7D supports&amp;nbsp;16/32-bit DDR3L/LPDDR2/LPDDR3-1066 memories.&lt;/P&gt;
&lt;P&gt;You can configure this directly in RPA when doing the DDR stress test.&lt;/P&gt;
&lt;P&gt;Best regards.&lt;/P&gt;</description>
      <pubDate>Tue, 02 Dec 2025 15:34:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX7D-16-bit-DDR3-Implementation-Issue/m-p/2253319#M242576</guid>
      <dc:creator>JorgeCas</dc:creator>
      <dc:date>2025-12-02T15:34:48Z</dc:date>
    </item>
    <item>
      <title>Re: iMX7D 16-bit DDR3 Implementation Issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX7D-16-bit-DDR3-Implementation-Issue/m-p/2253836#M242593</link>
      <description>&lt;P&gt;Thanks for quick reply!&lt;/P&gt;&lt;P&gt;As my understanding, the ds file generated by MX7D_DDR3_Register_Programming_Aid_V1_3 can been used to setup 16-bit DDR3(single chip). Is that right?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Cheng Shi&lt;/P&gt;</description>
      <pubDate>Wed, 03 Dec 2025 07:49:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX7D-16-bit-DDR3-Implementation-Issue/m-p/2253836#M242593</guid>
      <dc:creator>x10</dc:creator>
      <dc:date>2025-12-03T07:49:13Z</dc:date>
    </item>
    <item>
      <title>Re: iMX7D 16-bit DDR3 Implementation Issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX7D-16-bit-DDR3-Implementation-Issue/m-p/2254373#M242612</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;Yes, your understanding is correct.&lt;/P&gt;
&lt;P&gt;Best regards.&lt;/P&gt;</description>
      <pubDate>Wed, 03 Dec 2025 17:17:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX7D-16-bit-DDR3-Implementation-Issue/m-p/2254373#M242612</guid>
      <dc:creator>JorgeCas</dc:creator>
      <dc:date>2025-12-03T17:17:43Z</dc:date>
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