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    <title>i.MX Processors中的主题 Re: imx8mp 8GByte LPDDR4 definition</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-8GByte-LPDDR4-definition/m-p/2195151#M241757</link>
    <description>Hello Chavira.&lt;BR /&gt;Thank you for your help.&lt;BR /&gt;But first, to generate timing file, what values do we need to change for this memory in the table a sent before ?&lt;BR /&gt;Best regards and thank you&lt;BR /&gt;Angel</description>
    <pubDate>Wed, 29 Oct 2025 13:40:20 GMT</pubDate>
    <dc:creator>AngelF</dc:creator>
    <dc:date>2025-10-29T13:40:20Z</dc:date>
    <item>
      <title>imx8mp 8GByte LPDDR4 definition</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-8GByte-LPDDR4-definition/m-p/2195046#M241752</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;We have our own design based on imx8mp. Up to now we have been using 4GByte LPDDR4 and now we want to change to 8GByte LPDDR4 memory.&lt;/P&gt;&lt;P&gt;We use NXP excel to generate .ds file. Then with this .ds file and NXP DDR tool we generate lpddr4_timing.c file for u-boot.&lt;/P&gt;&lt;P&gt;Excel config parameters for 4GByte memory are&lt;/P&gt;&lt;TABLE border="0" cellspacing="0"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD height="18"&gt;Density per channel per chip select (Gb)1:&lt;/TD&gt;&lt;TD&gt;&lt;FONT face="Calibri"&gt;8&lt;/FONT&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD height="19"&gt;Number of Channels&lt;/TD&gt;&lt;TD&gt;&lt;STRONG&gt;&lt;FONT face="Calibri" color="#FA7D00"&gt;2&lt;/FONT&gt;&lt;/STRONG&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD height="19"&gt;Number of Chip Selects used2&lt;/TD&gt;&lt;TD&gt;2&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD height="18"&gt;Total DRAM density (Gb)&lt;/TD&gt;&lt;TD&gt;&lt;STRONG&gt;&lt;FONT face="Calibri" color="#FA7D00"&gt;32&lt;/FONT&gt;&lt;/STRONG&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD height="19"&gt;Number of ROW Addresses2&lt;/TD&gt;&lt;TD&gt;16&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD height="19"&gt;Number of COLUMN Addresses2&lt;/TD&gt;&lt;TD&gt;10&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD height="19"&gt;Number of BANK addresses2&lt;/TD&gt;&lt;TD&gt;3&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD height="18"&gt;Number of BANKS2&lt;/TD&gt;&lt;TD&gt;&lt;STRONG&gt;&lt;FONT face="Calibri" color="#FA7D00"&gt;8&lt;/FONT&gt;&lt;/STRONG&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD height="19"&gt;Bus Width&lt;/TD&gt;&lt;TD&gt;32&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD height="19"&gt;Clock Cycle Freq (MHz)3&lt;/TD&gt;&lt;TD&gt;1500&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD height="21"&gt;Clock Cycle Time (ns)&lt;/TD&gt;&lt;TD&gt;&lt;STRONG&gt;&lt;FONT face="Calibri" color="#FA7D00"&gt;0,666666666666667&lt;/FONT&gt;&lt;/STRONG&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD height="18"&gt;FREQ1 setpoint Clock Cycle Freq (MHz)&lt;/TD&gt;&lt;TD&gt;&lt;FONT face="Calibri"&gt;200&lt;/FONT&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD height="18"&gt;FREQ1 Clock Cycle Time (ns)&lt;/TD&gt;&lt;TD&gt;&lt;STRONG&gt;&lt;FONT face="Calibri" color="#FA7D00"&gt;5&lt;/FONT&gt;&lt;/STRONG&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD height="18"&gt;FREQ2 setpoint Clock Cycle Freq (MHz)&lt;/TD&gt;&lt;TD&gt;&lt;FONT face="Calibri"&gt;50&lt;/FONT&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD height="20"&gt;FREQ2 Clock Cycle Time (ns)&lt;/TD&gt;&lt;TD&gt;&lt;STRONG&gt;&lt;FONT face="Calibri" color="#FA7D00"&gt;20&lt;/FONT&gt;&lt;/STRONG&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;What do we need to change for this new 8GByte memory&amp;nbsp;(2 channels ×16 I/O × 2 ranks) ?&lt;/P&gt;&lt;P&gt;Best regards and thank you&lt;/P&gt;&lt;P&gt;Angel&lt;/P&gt;</description>
      <pubDate>Wed, 29 Oct 2025 10:26:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8mp-8GByte-LPDDR4-definition/m-p/2195046#M241752</guid>
      <dc:creator>AngelF</dc:creator>
      <dc:date>2025-10-29T10:26:45Z</dc:date>
    </item>
    <item>
      <title>Re: imx8mp 8GByte LPDDR4 definition</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-8GByte-LPDDR4-definition/m-p/2195134#M241756</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/190925"&gt;@AngelF&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;Thank you for contacting NXP Support!&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;After updating the device tree and timing file, you’ll also need to update the RAM size in your board’s U-Boot configuration file.&lt;/P&gt;
&lt;P&gt;&lt;A href="https://github.com/nxp-imx/uboot-imx/blob/lf_v2025.04/include/configs/imx8mp_evk.h" target="_self"&gt;imx8mp_evk.h (Example)&lt;/A&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;If you're using OP-TEE, make sure to update the RAM size in the corresponding configuration file as well.&lt;/P&gt;
&lt;P&gt;&lt;A href="https://github.com/nxp-imx/imx-optee-os/blob/788dc101b05ae47bfaa1a9e66ec620d6c0d9be19/core/arch/arm/plat-imx/conf.mk#L455" target="_self"&gt;conf.mk&lt;/A&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best regards,&lt;BR /&gt;Chavira&lt;/P&gt;</description>
      <pubDate>Wed, 29 Oct 2025 13:17:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8mp-8GByte-LPDDR4-definition/m-p/2195134#M241756</guid>
      <dc:creator>Chavira</dc:creator>
      <dc:date>2025-10-29T13:17:39Z</dc:date>
    </item>
    <item>
      <title>Re: imx8mp 8GByte LPDDR4 definition</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-8GByte-LPDDR4-definition/m-p/2195151#M241757</link>
      <description>Hello Chavira.&lt;BR /&gt;Thank you for your help.&lt;BR /&gt;But first, to generate timing file, what values do we need to change for this memory in the table a sent before ?&lt;BR /&gt;Best regards and thank you&lt;BR /&gt;Angel</description>
      <pubDate>Wed, 29 Oct 2025 13:40:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8mp-8GByte-LPDDR4-definition/m-p/2195151#M241757</guid>
      <dc:creator>AngelF</dc:creator>
      <dc:date>2025-10-29T13:40:20Z</dc:date>
    </item>
    <item>
      <title>Re: imx8mp 8GByte LPDDR4 definition</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-8GByte-LPDDR4-definition/m-p/2195158#M241759</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/190925"&gt;@AngelF&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;You should adjust those parameters based on the specific part number of the memory you're using.&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;The required specifications can be found in the datasheet for that memory component. Make sure to refer to it to ensure correct configuration.&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;Best regards,&lt;BR /&gt;Chavira&lt;/P&gt;</description>
      <pubDate>Wed, 29 Oct 2025 13:45:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8mp-8GByte-LPDDR4-definition/m-p/2195158#M241759</guid>
      <dc:creator>Chavira</dc:creator>
      <dc:date>2025-10-29T13:45:20Z</dc:date>
    </item>
    <item>
      <title>Re: imx8mp 8GByte LPDDR4 definition</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-8GByte-LPDDR4-definition/m-p/2195170#M241761</link>
      <description>Hello Chavira,&lt;BR /&gt;Yes, you are right, but I can not find the correct configuration.&lt;BR /&gt;Memory is MT53E2G32D4DE-046 AIT:C (2 Gig × 32 (2 channels ×16 I/O × 2 ranks))&lt;BR /&gt;In the above table only possibility is to change "Density per channel per chip select (Gb)1:" from 8 to 16 to get "Total DRAM density (Gb)" 64, but it is not working.&lt;BR /&gt;Definitions and devive tree are:&lt;BR /&gt;#define CONFIG_SYS_SDRAM_BASE 0x40000000&lt;BR /&gt;#define PHYS_SDRAM 0x40000000&lt;BR /&gt;#define PHYS_SDRAM_SIZE 0xC0000000&lt;BR /&gt;#define PHYS_SDRAM_2 0x100000000&lt;BR /&gt;#define PHYS_SDRAM_2_SIZE (SZ_4G + SZ_1G)&lt;BR /&gt;&lt;BR /&gt;memory@40000000 {&lt;BR /&gt;device_type = "memory";&lt;BR /&gt;reg = &amp;lt;0x0 0x40000000 0 0xc0000000&amp;gt;,&lt;BR /&gt;&amp;lt;0x1 0x00000000 1 0x40000000&amp;gt;;&lt;BR /&gt;};&lt;BR /&gt;Could you please help us to get the right configuration ?&lt;BR /&gt;Best regards and thank you&lt;BR /&gt;Angel</description>
      <pubDate>Wed, 29 Oct 2025 14:23:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8mp-8GByte-LPDDR4-definition/m-p/2195170#M241761</guid>
      <dc:creator>AngelF</dc:creator>
      <dc:date>2025-10-29T14:23:52Z</dc:date>
    </item>
    <item>
      <title>Re: imx8mp 8GByte LPDDR4 definition</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-8GByte-LPDDR4-definition/m-p/2195274#M241765</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/190925"&gt;@AngelF&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The following values are used to configure 8GB of RAM:&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;PRE&gt;&lt;CODE&gt;#define PHYS_SDRAM_2_SIZE 0x140000000&lt;/CODE&gt;&lt;/PRE&gt;
&lt;PRE&gt;&lt;CODE&gt;memory@40000000 {
    device_type = "memory";
    reg = &amp;lt;0x0 0x40000000 0 0xc0000000&amp;gt;,
          &amp;lt;0x1 0x00000000 0 0x140000000&amp;gt;;
};&lt;/CODE&gt;&lt;/PRE&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The i.MX8MP platform supports two memory regions:&lt;/P&gt;
&lt;P&gt;The first region starts at 0x40000000 and has a size of 3GB.&lt;BR /&gt;The second region starts at 0x100000000 and covers the remaining 5GB.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Chavira_0-1761762398605.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/363129iFF7A0E36415DBA9B/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Chavira_0-1761762398605.png" alt="Chavira_0-1761762398605.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;Best regards,&lt;BR /&gt;Chavira&lt;/P&gt;</description>
      <pubDate>Wed, 29 Oct 2025 18:27:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8mp-8GByte-LPDDR4-definition/m-p/2195274#M241765</guid>
      <dc:creator>Chavira</dc:creator>
      <dc:date>2025-10-29T18:27:04Z</dc:date>
    </item>
    <item>
      <title>Re: imx8mp 8GByte LPDDR4 definition</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-8GByte-LPDDR4-definition/m-p/2195554#M241780</link>
      <description>Hello Chavira,&lt;BR /&gt;Thank you for your answer.&lt;BR /&gt;Yes, you are right, but I am asking about values to set in file MX8M_LPDDR4_RPA_v33.xlsx from NXP. With these values we generate the initialization script to load with NXP DDR tool.&lt;BR /&gt;We need it to generate lpddr4_timing.c file.&lt;BR /&gt;Values we sent in our first post are for 4GByte memory and we need new values for the 8GByte memory MT53E2G32D4DE-046 AIT:C (2 Gig × 32 (2 channels ×16 I/O × 2 ranks))&lt;BR /&gt;&lt;BR /&gt;Best regards and thank you&lt;BR /&gt;Angel</description>
      <pubDate>Thu, 30 Oct 2025 07:02:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8mp-8GByte-LPDDR4-definition/m-p/2195554#M241780</guid>
      <dc:creator>AngelF</dc:creator>
      <dc:date>2025-10-30T07:02:48Z</dc:date>
    </item>
    <item>
      <title>Re: imx8mp 8GByte LPDDR4 definition</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-8GByte-LPDDR4-definition/m-p/2195909#M241794</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/190925"&gt;@AngelF&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;According to the datasheet the correct parameters should be the next:&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;
&lt;TABLE width="326"&gt;
&lt;TBODY&gt;
&lt;TR&gt;
&lt;TD width="262"&gt;Parameter&lt;/TD&gt;
&lt;TD width="64"&gt;Value&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR&gt;
&lt;TD&gt;Density per channel per chip select (Gb)&lt;/TD&gt;
&lt;TD&gt;16&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR&gt;
&lt;TD&gt;Number of Channels&lt;/TD&gt;
&lt;TD&gt;2&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR&gt;
&lt;TD&gt;Number of Chip Selects used&lt;/TD&gt;
&lt;TD&gt;2&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR&gt;
&lt;TD&gt;Total DRAM density (Gb)&lt;/TD&gt;
&lt;TD&gt;64&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR&gt;
&lt;TD&gt;Number of ROW Addresses&lt;/TD&gt;
&lt;TD&gt;16&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR&gt;
&lt;TD&gt;Number of COLUMN Addresses&lt;/TD&gt;
&lt;TD&gt;10&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR&gt;
&lt;TD&gt;Number of BANK addresses&lt;/TD&gt;
&lt;TD&gt;3&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR&gt;
&lt;TD&gt;Number of BANKS&lt;/TD&gt;
&lt;TD&gt;8&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR&gt;
&lt;TD&gt;Bus Width&lt;/TD&gt;
&lt;TD&gt;32&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR&gt;
&lt;TD&gt;Clock Cycle Freq (MHz)&lt;/TD&gt;
&lt;TD&gt;2133&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR&gt;
&lt;TD&gt;Clock Cycle Time (ns)&lt;/TD&gt;
&lt;TD&gt;0.468823&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR&gt;
&lt;TD&gt;FREQ1 setpoint Clock Cycle Freq (MHz)&lt;/TD&gt;
&lt;TD&gt;200&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR&gt;
&lt;TD&gt;FREQ1 Clock Cycle Time (ns)&lt;/TD&gt;
&lt;TD&gt;5&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR&gt;
&lt;TD&gt;FREQ2 setpoint Clock Cycle Freq (MHz)&lt;/TD&gt;
&lt;TD&gt;50&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR&gt;
&lt;TD&gt;FREQ2 Clock Cycle Time (ns)&lt;/TD&gt;
&lt;TD&gt;20&lt;/TD&gt;
&lt;/TR&gt;
&lt;/TBODY&gt;
&lt;/TABLE&gt;</description>
      <pubDate>Thu, 30 Oct 2025 14:47:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8mp-8GByte-LPDDR4-definition/m-p/2195909#M241794</guid>
      <dc:creator>Chavira</dc:creator>
      <dc:date>2025-10-30T14:47:06Z</dc:date>
    </item>
    <item>
      <title>Re: imx8mp 8GByte LPDDR4 definition</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-8GByte-LPDDR4-definition/m-p/2196460#M241826</link>
      <description>Hello Chavira,&lt;BR /&gt;Thank you for your help.&lt;BR /&gt;Just one thing to point. For this memory to work also "Number of ROW Addresses" must be set from 16 to 17.&lt;BR /&gt;The problem is that MX8M_LPDDR4_RPA_v33.xlsx from NXP download site does not allow to set this field to 17. Only values from 13 to 16 are allowed.&lt;BR /&gt;I had to use an older version of this tool that allows to set 17 in this field.&lt;BR /&gt;Best regards and thank you&lt;BR /&gt;Angel</description>
      <pubDate>Fri, 31 Oct 2025 08:01:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8mp-8GByte-LPDDR4-definition/m-p/2196460#M241826</guid>
      <dc:creator>AngelF</dc:creator>
      <dc:date>2025-10-31T08:01:11Z</dc:date>
    </item>
    <item>
      <title>Re: imx8mp 8GByte LPDDR4 definition</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-8GByte-LPDDR4-definition/m-p/2196708#M241837</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/190925"&gt;@AngelF&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Try downloading the &lt;A href="https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/config-tools-for-i-mx-applications-processors:CONFIG-TOOLS-IMX" target="_self"&gt;Config Tools for i.MX Applications Processors&lt;/A&gt;, in that tool we have an updated DDR Tool to generate the proper files easily.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Chavira_0-1761919936500.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/363517i6DFED84BDAEC2084/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Chavira_0-1761919936500.png" alt="Chavira_0-1761919936500.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;BR /&gt;Chavira&lt;/P&gt;</description>
      <pubDate>Fri, 31 Oct 2025 14:12:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8mp-8GByte-LPDDR4-definition/m-p/2196708#M241837</guid>
      <dc:creator>Chavira</dc:creator>
      <dc:date>2025-10-31T14:12:29Z</dc:date>
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