topic Inline ECC support MIMX8DL1AVNFZAB in i.MX Processors

Inline ECC support MIMX8DL1AVNFZAB

Ramesh_M — Sat, 25 Oct 2025 12:17:21 GMT

Hello,

We are using MT53D512M16D1DS-046AAT:D(1GB density) in our custom carrier board. Now that part is EOL and we have found the same footprint drop in replacement part MT53E768M16D1ZW-046AAT:C (1.5GB) with longevity support . Can you help to clarify the following queries

As per i.MX8DualXL DDR Controller Configuration Spreadsheet v1.26 for non-binary aligned density inline ECC functionality not supported by i.Mx8DualXL

Now we are in the start of production, Is there any work around available to support the in-line ECC with 1.5GB part ?
Can we still use the 1.5GB part as 1GB part? (If the 1.5GB memory is configured as 1GB memory in DDR tool, So that i.Mx8DualXL can treat this part as 1GB part. Hence in-line ECC will be supported) Is that possible ?

Thanks in advance.

#LPDDR4 #MIMX8DL1AVNFZAB #ECC

Re: Inline ECC support MIMX8DL1AVNFZAB

Bio_TICFSL — Mon, 27 Oct 2025 14:09:42 GMT

Hello,

The i.MX8DualXL processor does not support inline ECC functionality for non-binary aligned memory densities. This is confirmed in the i.MX8DualXL DDR Controller Configuration Spreadsheet v1.26 that you referenced.

Your current memory (MT53D512M16D1DS-046AAT:D with 1GB density) is being replaced with MT53E768M16D1ZW-046AAT:C which has 1.5GB density. This 1.5GB density is non-binary aligned, and therefore inline ECC cannot be supported with this memory configuration on the i.MX8DualXL.

The limitation is due to the hardware design of the DDR controller in the i.MX8DualXL. For ECC functionality, binary aligned memory densities (such as 1GB, 2GB, 4GB) are required.

If ECC functionality is critical for your application, you would need to consider using a binary aligned memory density that is compatible with your i.MX8DualXL processor.

regards