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    <title>i.MX Processors中的主题 Re: LPDDR4x memory size configuration</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR4x-memory-size-configuration/m-p/2190963#M241586</link>
    <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/245887"&gt;@bora&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;Thank you for contacting NXP Support!&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The original custom configuration is wrong because it defines CMA’s alloc-ranges to cover the entire DDR (0x80000000–0x9FFFFFFF) while also reserving Ethos-U at 0x80000000–0x81FFFFFF and ELE at 0x84120000, creating overlaps. Additionally, Ethos-U is marked as reusable without no-map, allowing the kernel to reuse that memory, and ELE is not explicitly linked to its driver via memory-region. This breaks memory isolation, can cause corruption and DMA errors, and does not follow NXP’s best practices, which always separate CMA from dedicated pools and place ELE in a safe block outside CMA.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Try the next recommendation:&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;LI-CODE lang="markup"&gt;    reserved-memory {
        #address-cells = &amp;lt;2&amp;gt;;
        #size-cells   = &amp;lt;2&amp;gt;;
        ranges;

        ethosu_mem: ethosu_region@80000000 {
            compatible = "shared-dma-pool";
            reg = &amp;lt;0 0x80000000 0 0x02000000&amp;gt;;
            no-map;   
        };

        linux,cma {
            compatible = "shared-dma-pool";
            reusable;
            alloc-ranges = &amp;lt;0 0x82000000 0 0x1E000000&amp;gt;;
			size = &amp;lt;0 0x04000000&amp;gt;;
            linux,cma-default;
        };
        vdev0vring0: vdev0vring0@84000000 { reg = &amp;lt;0 0x84000000 0 0x00008000&amp;gt;; no-map; }; /* 32KB */
        vdev0vring1: vdev0vring1@84008000 { reg = &amp;lt;0 0x84008000 0 0x00008000&amp;gt;; no-map; }; /* 32KB */
        vdev1vring0: vdev1vring0@84010000 { reg = &amp;lt;0 0x84010000 0 0x00008000&amp;gt;; no-map; }; /* 32KB */
        vdev1vring1: vdev1vring1@84018000 { reg = &amp;lt;0 0x84018000 0 0x00008000&amp;gt;; no-map; }; /* 32KB */

        vdevbuffer: vdevbuffer@84020000 {
            compatible = "shared-dma-pool";
            reg = &amp;lt;0 0x84020000 0 0x00100000&amp;gt;;
            no-map;
        };

        ele_reserved: ele-reserved@90000000 {
            compatible = "shared-dma-pool";
            reg = &amp;lt;0 0x90000000 0 0x00100000&amp;gt;; 
            no-map;
        };
    };&lt;/LI-CODE&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;If you are using optee you should update the ddr size in the next file too:&lt;BR /&gt;&lt;BR /&gt;&lt;A href="https://github.com/nxp-imx/imx-optee-os/blob/e0a3e77735941e6057a1994a576b83a93ea0bdb9/core/arch/arm/plat-imx/conf.mk#L457" target="_blank"&gt;https://github.com/nxp-imx/imx-optee-os/blob/e0a3e77735941e6057a1994a576b83a93ea0bdb9/core/arch/arm/plat-imx/conf.mk#L457&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;BR /&gt;Chavira&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Wed, 22 Oct 2025 18:56:04 GMT</pubDate>
    <dc:creator>Chavira</dc:creator>
    <dc:date>2025-10-22T18:56:04Z</dc:date>
    <item>
      <title>LPDDR4x memory size configuration</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR4x-memory-size-configuration/m-p/2190760#M241572</link>
      <description>&lt;P&gt;I use imx93 for my custom board and with&amp;nbsp;MT53E256M16D1 LPDDR4X RAM. I changed in the device tree&amp;nbsp;&lt;/P&gt;&lt;LI-CODE lang="markup"&gt;reserved-memory {
		#address-cells = &amp;lt;2&amp;gt;;
		#size-cells = &amp;lt;2&amp;gt;;
		ranges;

		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			alloc-ranges = &amp;lt;0 0x80000000 0 0x20000000&amp;gt;;
			size = &amp;lt;0 0x02000000&amp;gt;;
			linux,cma-default;
		};

		ethosu_mem: ethosu_region@80000000 {
			compatible = "shared-dma-pool";
			reusable;
			reg = &amp;lt;0x0 0x80000000 0x0 0x02000000&amp;gt;;
		};

		vdev0vring0: vdev0vring0@84000000 {
			reg = &amp;lt;0 0x84000000 0 0x8000&amp;gt;;
			no-map;
		};

		vdev0vring1: vdev0vring1@84008000 {
			reg = &amp;lt;0 0x84008000 0 0x8000&amp;gt;;
			no-map;
		};

		vdev1vring0: vdev1vring0@84010000 {
			reg = &amp;lt;0 0x84010000 0 0x8000&amp;gt;;
			no-map;
		};

		vdev1vring1: vdev1vring1@84018000 {
			reg = &amp;lt;0 0x84018000 0 0x8000&amp;gt;;
			no-map;
		};

		rsc_table: rsc-table@2021e000 {
			reg = &amp;lt;0 0x2021e000 0 0x1000&amp;gt;;
			no-map;
		};

		vdevbuffer: vdevbuffer@84020000 {
			compatible = "shared-dma-pool";
			reg = &amp;lt;0 0x84020000 0 0x100000&amp;gt;;
			no-map;
		};

		ele_reserved: ele-reserved@84120000 {
			compatible = "shared-dma-pool";
			reg = &amp;lt;0 0x84120000 0 0x100000&amp;gt;;
			no-map;
		};
	};&lt;/LI-CODE&gt;&lt;P&gt;and in the u-boot I use this header file imx93_evk.h and changed only&amp;nbsp;define PHYS_SDRAM_SIZE&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;but some how I still get memory errors. do I need to change anything ?&lt;/P&gt;</description>
      <pubDate>Wed, 22 Oct 2025 11:47:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR4x-memory-size-configuration/m-p/2190760#M241572</guid>
      <dc:creator>bora</dc:creator>
      <dc:date>2025-10-22T11:47:31Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR4x memory size configuration</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR4x-memory-size-configuration/m-p/2190963#M241586</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/245887"&gt;@bora&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;Thank you for contacting NXP Support!&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The original custom configuration is wrong because it defines CMA’s alloc-ranges to cover the entire DDR (0x80000000–0x9FFFFFFF) while also reserving Ethos-U at 0x80000000–0x81FFFFFF and ELE at 0x84120000, creating overlaps. Additionally, Ethos-U is marked as reusable without no-map, allowing the kernel to reuse that memory, and ELE is not explicitly linked to its driver via memory-region. This breaks memory isolation, can cause corruption and DMA errors, and does not follow NXP’s best practices, which always separate CMA from dedicated pools and place ELE in a safe block outside CMA.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Try the next recommendation:&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;LI-CODE lang="markup"&gt;    reserved-memory {
        #address-cells = &amp;lt;2&amp;gt;;
        #size-cells   = &amp;lt;2&amp;gt;;
        ranges;

        ethosu_mem: ethosu_region@80000000 {
            compatible = "shared-dma-pool";
            reg = &amp;lt;0 0x80000000 0 0x02000000&amp;gt;;
            no-map;   
        };

        linux,cma {
            compatible = "shared-dma-pool";
            reusable;
            alloc-ranges = &amp;lt;0 0x82000000 0 0x1E000000&amp;gt;;
			size = &amp;lt;0 0x04000000&amp;gt;;
            linux,cma-default;
        };
        vdev0vring0: vdev0vring0@84000000 { reg = &amp;lt;0 0x84000000 0 0x00008000&amp;gt;; no-map; }; /* 32KB */
        vdev0vring1: vdev0vring1@84008000 { reg = &amp;lt;0 0x84008000 0 0x00008000&amp;gt;; no-map; }; /* 32KB */
        vdev1vring0: vdev1vring0@84010000 { reg = &amp;lt;0 0x84010000 0 0x00008000&amp;gt;; no-map; }; /* 32KB */
        vdev1vring1: vdev1vring1@84018000 { reg = &amp;lt;0 0x84018000 0 0x00008000&amp;gt;; no-map; }; /* 32KB */

        vdevbuffer: vdevbuffer@84020000 {
            compatible = "shared-dma-pool";
            reg = &amp;lt;0 0x84020000 0 0x00100000&amp;gt;;
            no-map;
        };

        ele_reserved: ele-reserved@90000000 {
            compatible = "shared-dma-pool";
            reg = &amp;lt;0 0x90000000 0 0x00100000&amp;gt;; 
            no-map;
        };
    };&lt;/LI-CODE&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;If you are using optee you should update the ddr size in the next file too:&lt;BR /&gt;&lt;BR /&gt;&lt;A href="https://github.com/nxp-imx/imx-optee-os/blob/e0a3e77735941e6057a1994a576b83a93ea0bdb9/core/arch/arm/plat-imx/conf.mk#L457" target="_blank"&gt;https://github.com/nxp-imx/imx-optee-os/blob/e0a3e77735941e6057a1994a576b83a93ea0bdb9/core/arch/arm/plat-imx/conf.mk#L457&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;BR /&gt;Chavira&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 22 Oct 2025 18:56:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR4x-memory-size-configuration/m-p/2190963#M241586</guid>
      <dc:creator>Chavira</dc:creator>
      <dc:date>2025-10-22T18:56:04Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR4x memory size configuration</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR4x-memory-size-configuration/m-p/2192394#M241628</link>
      <description>Thank you for the configuration now gallium softpipe works for the qt6, but how can I make it work via llvmpipe ? I still get segmentation fault, do you know maybe the packages I need to install?</description>
      <pubDate>Fri, 24 Oct 2025 08:26:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR4x-memory-size-configuration/m-p/2192394#M241628</guid>
      <dc:creator>bora</dc:creator>
      <dc:date>2025-10-24T08:26:19Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR4x memory size configuration</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR4x-memory-size-configuration/m-p/2192636#M241639</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/245887"&gt;@bora&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;I haven’t used LLVMpipe personally, but based on what I found online, the limited amount of RAM on your board might be the issue. Since LLVMpipe performs 3D rendering using the CPU instead of a GPU, it typically requires more memory to handle the workload efficiently. With low RAM, the system may struggle to render graphics smoothly.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 24 Oct 2025 16:07:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR4x-memory-size-configuration/m-p/2192636#M241639</guid>
      <dc:creator>Chavira</dc:creator>
      <dc:date>2025-10-24T16:07:21Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR4x memory size configuration</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR4x-memory-size-configuration/m-p/2194175#M241714</link>
      <description>I get this error :&lt;BR /&gt;root@imx93-11x11-lpddr4x-evk:/usr/share/examples/widgets/widgets/calendarwidget/bin# dmesg | grep fdt&lt;BR /&gt;[ 0.000000] OF: fdt: Reserved memory: failed to reserve memory for node 'ethosu_region@80000000': base 0x0000000080000000, size 32 MiB&lt;BR /&gt;&lt;BR /&gt;is it relevant ?</description>
      <pubDate>Tue, 28 Oct 2025 09:27:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR4x-memory-size-configuration/m-p/2194175#M241714</guid>
      <dc:creator>bora</dc:creator>
      <dc:date>2025-10-28T09:27:52Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR4x memory size configuration</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR4x-memory-size-configuration/m-p/2194413#M241726</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/245887"&gt;@bora&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I tested the following &lt;STRONG&gt;Device Tree configuration &lt;/STRONG&gt;using the iMX93-FRDM board:&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;
&lt;LI-CODE lang="markup"&gt;	reserved-memory {
        #address-cells = &amp;lt;2&amp;gt;;
        #size-cells   = &amp;lt;2&amp;gt;;
        ranges;

        linux,cma {
            compatible = "shared-dma-pool";
            reg = &amp;lt;0 0x88000000 0 0x04000000&amp;gt;;   /* 64 MB @ 0x8800_0000 */
            reusable;
            linux,cma-default;
        };

        /* Ethos-U: mover lejos del arranque del kernel (32 MB) */
        ethosu_mem: ethosu_region@8c000000 {
            compatible = "shared-dma-pool";
            reg = &amp;lt;0 0x8c000000 0 0x02000000&amp;gt;;   
            no-map;                               
        };

        vdev0vring0: vdev0vring0@84000000 { reg = &amp;lt;0 0x84000000 0 0x00008000&amp;gt;; no-map; };
        vdev0vring1: vdev0vring1@84008000 { reg = &amp;lt;0 0x84008000 0 0x00008000&amp;gt;; no-map; };
        vdev1vring0: vdev1vring0@84010000 { reg = &amp;lt;0 0x84010000 0 0x00008000&amp;gt;; no-map; };
        vdev1vring1: vdev1vring1@84018000 { reg = &amp;lt;0 0x84018000 0 0x00008000&amp;gt;; no-map; };

        rsc_table: rsc-table@2021e000 { reg = &amp;lt;0 0x2021e000 0 0x00001000&amp;gt;; no-map; }; /* OCRAM */

        vdevbuffer: vdevbuffer@84020000 {
            compatible = "shared-dma-pool";
            reg = &amp;lt;0 0x84020000 0 0x00100000&amp;gt;;   /* 1 MB */
            no-map;
        };

        ele_reserved: ele-reserved@90000000 {
            compatible = "shared-dma-pool";
            reg = &amp;lt;0 0x90000000 0 0x00100000&amp;gt;;   /* 1 MB @ 0x9000_0000 */
            no-map;
        };
    };&lt;/LI-CODE&gt;
&lt;P&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;
&lt;P&gt;No errors are observed:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Chavira_0-1761666429986.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/362913i03EFE432D44DB28F/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Chavira_0-1761666429986.png" alt="Chavira_0-1761666429986.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Chavira_1-1761666458518.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/362914i8D121861DD4CAB3C/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Chavira_1-1761666458518.png" alt="Chavira_1-1761666458518.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;/P&gt;
&lt;P&gt;Chavira&lt;/P&gt;</description>
      <pubDate>Tue, 28 Oct 2025 15:49:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR4x-memory-size-configuration/m-p/2194413#M241726</guid>
      <dc:creator>Chavira</dc:creator>
      <dc:date>2025-10-28T15:49:26Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR4x memory size configuration</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR4x-memory-size-configuration/m-p/2194812#M241748</link>
      <description>Hi Chavira which RAM do you use? I got on my board this one&lt;BR /&gt;&lt;A href="https://www.micron.com/products/memory/dram-components/lpddr4/part-catalog/part-detail/mt53e256m16d1ds-046-wt-b" target="_blank"&gt;https://www.micron.com/products/memory/dram-components/lpddr4/part-catalog/part-detail/mt53e256m16d1ds-046-wt-b&lt;/A&gt;</description>
      <pubDate>Wed, 29 Oct 2025 06:18:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR4x-memory-size-configuration/m-p/2194812#M241748</guid>
      <dc:creator>bora</dc:creator>
      <dc:date>2025-10-29T06:18:32Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR4x memory size configuration</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR4x-memory-size-configuration/m-p/2195126#M241755</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/245887"&gt;@bora&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;We have installed the &lt;STRONG&gt;MT53E1G16D1FW-046&lt;/STRONG&gt; memory module on the &lt;STRONG&gt;FRDM board&lt;/STRONG&gt;.&lt;/P&gt;
&lt;P&gt;I've configured both &lt;STRONG&gt;U-Boot&lt;/STRONG&gt; and the &lt;STRONG&gt;Linux Kernel&lt;/STRONG&gt; to utilize &lt;STRONG&gt;512MB&lt;/STRONG&gt; of memory.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best regards,&lt;BR /&gt;Chavira&lt;/P&gt;</description>
      <pubDate>Wed, 29 Oct 2025 13:00:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR4x-memory-size-configuration/m-p/2195126#M241755</guid>
      <dc:creator>Chavira</dc:creator>
      <dc:date>2025-10-29T13:00:46Z</dc:date>
    </item>
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