<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックRe: Quad Max Memory map (SDRAM) NXP i.MX8QM RevB</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Quad-Max-Memory-map-SDRAM-NXP-i-MX8QM-RevB/m-p/2189237#M241511</link>
    <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;DIV style="display: contents;" data-subtree="aimfl,mfl"&gt;The i.MX 8QuadMax doesn't have a single "memory map" document available publicly, but&lt;/DIV&gt;
&lt;P&gt;&lt;MARK class="HxTRcb"&gt;its memory is organized by external interfaces like LPDDR4&amp;nbsp;which is the primary high-speed system memory, and various storage options such as eMMC, SD card interfaces, and Qual/SPI/ Octal SPI&lt;STRONG&gt;&amp;nbsp;&lt;/STRONG&gt;NOR Flash&lt;/MARK&gt;. The i.MX 8QuadMax also includes on-chip memory for Boot ROM (128 KB) and on-chip RAM (128 KB + 32 KB). The specific memory addresses for these components are detailed in the detailed technical documentation provided by NXP, but the general structure is defined by the system-level layout and the memory controller interfaces.&lt;SPAN class="uJ19be notranslate" data-wiz-uids="mSxUZe_l,mSxUZe_m"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN class="uJ19be notranslate" data-wiz-uids="mSxUZe_l,mSxUZe_m"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic=""&gt;You can check previous thread with auth_cntr fail that appears is the same situation like yours:&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN class="uJ19be notranslate" data-wiz-uids="mSxUZe_l,mSxUZe_m"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic=""&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/Should-auth-cntr-provide-a-return-value/m-p/2138272" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors/Should-auth-cntr-provide-a-return-value/m-p/2138272&lt;/A&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN class="uJ19be notranslate" data-wiz-uids="mSxUZe_l,mSxUZe_m"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic=""&gt;regards&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Mon, 20 Oct 2025 14:09:24 GMT</pubDate>
    <dc:creator>Bio_TICFSL</dc:creator>
    <dc:date>2025-10-20T14:09:24Z</dc:date>
    <item>
      <title>Quad Max Memory map (SDRAM) NXP i.MX8QM RevB</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Quad-Max-Memory-map-SDRAM-NXP-i-MX8QM-RevB/m-p/2186780#M241437</link>
      <description>&lt;P&gt;I cannot find the memory map for RAM in the reference manual or the "SRM".&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Trying to see where the ranges are size wise, best place to load the kernel for signed kernel, then where to have auth_cntr move it to.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;</description>
      <pubDate>Wed, 15 Oct 2025 16:15:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Quad-Max-Memory-map-SDRAM-NXP-i-MX8QM-RevB/m-p/2186780#M241437</guid>
      <dc:creator>flobro</dc:creator>
      <dc:date>2025-10-15T16:15:18Z</dc:date>
    </item>
    <item>
      <title>Re: Quad Max Memory map (SDRAM) NXP i.MX8QM RevB</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Quad-Max-Memory-map-SDRAM-NXP-i-MX8QM-RevB/m-p/2189237#M241511</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;DIV style="display: contents;" data-subtree="aimfl,mfl"&gt;The i.MX 8QuadMax doesn't have a single "memory map" document available publicly, but&lt;/DIV&gt;
&lt;P&gt;&lt;MARK class="HxTRcb"&gt;its memory is organized by external interfaces like LPDDR4&amp;nbsp;which is the primary high-speed system memory, and various storage options such as eMMC, SD card interfaces, and Qual/SPI/ Octal SPI&lt;STRONG&gt;&amp;nbsp;&lt;/STRONG&gt;NOR Flash&lt;/MARK&gt;. The i.MX 8QuadMax also includes on-chip memory for Boot ROM (128 KB) and on-chip RAM (128 KB + 32 KB). The specific memory addresses for these components are detailed in the detailed technical documentation provided by NXP, but the general structure is defined by the system-level layout and the memory controller interfaces.&lt;SPAN class="uJ19be notranslate" data-wiz-uids="mSxUZe_l,mSxUZe_m"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN class="uJ19be notranslate" data-wiz-uids="mSxUZe_l,mSxUZe_m"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic=""&gt;You can check previous thread with auth_cntr fail that appears is the same situation like yours:&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN class="uJ19be notranslate" data-wiz-uids="mSxUZe_l,mSxUZe_m"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic=""&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/Should-auth-cntr-provide-a-return-value/m-p/2138272" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors/Should-auth-cntr-provide-a-return-value/m-p/2138272&lt;/A&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN class="uJ19be notranslate" data-wiz-uids="mSxUZe_l,mSxUZe_m"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic=""&gt;regards&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 20 Oct 2025 14:09:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Quad-Max-Memory-map-SDRAM-NXP-i-MX8QM-RevB/m-p/2189237#M241511</guid>
      <dc:creator>Bio_TICFSL</dc:creator>
      <dc:date>2025-10-20T14:09:24Z</dc:date>
    </item>
    <item>
      <title>Re: Quad Max Memory map (SDRAM) NXP i.MX8QM RevB</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Quad-Max-Memory-map-SDRAM-NXP-i-MX8QM-RevB/m-p/2195811#M241789</link>
      <description>&lt;P&gt;The real question should have been:&lt;/P&gt;&lt;P&gt;What is the RAM memory layout with uboot loaded, to avoid stepping on any important locations when loading Linux and the device tree?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 30 Oct 2025 12:09:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Quad-Max-Memory-map-SDRAM-NXP-i-MX8QM-RevB/m-p/2195811#M241789</guid>
      <dc:creator>flobro</dc:creator>
      <dc:date>2025-10-30T12:09:45Z</dc:date>
    </item>
  </channel>
</rss>

