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    <title>topic Re: imx8mp flexcan hardware timestamp in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-flexcan-hardware-timestamp/m-p/2179809#M241135</link>
    <description>&lt;UL&gt;&lt;LI&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;Default 16-bit timer:&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN&gt;&amp;nbsp;The FlexCAN module has a built-in 16-bit timer that counts the bit intervals on the CAN bus.&lt;/SPAN&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;SPAN&gt;And has a nasty feature that every time CAN clock synchronization takes place, this 16-bit timer clock period is affected a bit. Not all of this 16-bit timer periods are equal to bit time. So if you try to use some other on-SoC timer (with clock derived from the same clock parent as CAN clock) to count 16-bit timer overflows to extend the width of timestamp clock, you will need to somehow track the drift of timestamp clock due to CAN receive traffic.&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Fri, 03 Oct 2025 09:02:59 GMT</pubDate>
    <dc:creator>kef2</dc:creator>
    <dc:date>2025-10-03T09:02:59Z</dc:date>
    <item>
      <title>imx8mp flexcan hardware timestamp</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-flexcan-hardware-timestamp/m-p/2179286#M241105</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;We have our own design based on imx8mp and kernel 6.6.23 from NXP.&lt;/P&gt;&lt;P&gt;We are using both flexcan interfaces and we would like to read hardware timestamp from driver. We are using candump but always read 0&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;candump -H -L&lt;BR /&gt;(0000000000.000000) canfd1 776#94CD03004FC7E1&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Do you know how we can enable this feature?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Best regards and thank you&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Angel&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 02 Oct 2025 11:01:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8mp-flexcan-hardware-timestamp/m-p/2179286#M241105</guid>
      <dc:creator>AngelF</dc:creator>
      <dc:date>2025-10-02T11:01:19Z</dc:date>
    </item>
    <item>
      <title>Re: imx8mp flexcan hardware timestamp</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-flexcan-hardware-timestamp/m-p/2179382#M241116</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;DIV style="display: contents;" data-subtree="aimfl" data-processed="true"&gt;The i.MX 8M Plus&amp;nbsp;FlexCAN has a hardware timestamp feature that &amp;nbsp;&lt;MARK class="HxTRcb" data-processed="true"&gt;uses a free-running 16-bit timer, which increments with each bit interval based on the CAN baud rate and resets on the reception of each CAN frame by default&lt;/MARK&gt;. To get a more accurate timestamp and overcome limitations, you must enable High-Resolution (HR) Timestamp in the FlexCAN Control Register 1. This requires a separate, external timer source, often a System Timer (STM), which you configure to provide a high-resolution time base.&lt;SPAN class="uJ19be notranslate" data-wiz-uids="Yqxuse_n,Yqxuse_o" data-processed="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAIQAA" data-processed="true"&gt;How it works&lt;/DIV&gt;
&lt;DIV class="Fsg96" data-sfc-cp="" data-processed="true"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;UL class="W4TX6e" data-sfc-cp="" data-processed="true"&gt;
&lt;LI&gt;&lt;SPAN class="ymCSIb" data-hveid="CAMQAA"&gt;&lt;SPAN class="dsyJjd"&gt;&lt;SPAN class="T286Pc" data-sfc-cp=""&gt;Default 16-bit timer:&lt;/SPAN&gt;&lt;/SPAN&gt; The FlexCAN module has a built-in 16-bit timer that counts the bit intervals on the CAN bus.&lt;/SPAN&gt;
&lt;UL class="U6u95"&gt;
&lt;LI data-hveid="CAMQAQ"&gt;&lt;SPAN class="T286Pc" data-sfc-cp=""&gt;This timer wraps around (overflows) after 65535 clock ticks.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAMQAg"&gt;&lt;SPAN class="T286Pc" data-sfc-cp=""&gt;The time it takes to overflow depends on the CAN bus speed.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAMQAw"&gt;&lt;SPAN class="T286Pc" data-sfc-cp=""&gt;You can set &lt;CODE class="o8j0Mc"&gt;CRTL1[TSYN]&lt;/CODE&gt; to '1' to automatically reset the timer upon receiving a frame, which is useful for maintaining message order but still subject to the 16-bit limit.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAMQAw"&gt;&lt;SPAN class="ymCSIb" data-hveid="CAMQBQ"&gt;&lt;SPAN class="dsyJjd"&gt;&lt;SPAN class="T286Pc" data-sfc-cp=""&gt;High-Resolution (HR) timestamp:&lt;/SPAN&gt;&lt;/SPAN&gt; To achieve higher precision, you enable the HR timestamp feature by setting the relevant bit in the FlexCAN control register.&lt;/SPAN&gt;
&lt;UL class="U6u95"&gt;
&lt;LI data-hveid="CAMQBg"&gt;&lt;SPAN class="T286Pc" data-sfc-cp=""&gt;This disables the internal 16-bit timer for timestamping.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAMQBw"&gt;&lt;SPAN class="T286Pc" data-sfc-cp=""&gt;It enables the use of an external timer source, such as an STM, for timestamping.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAMQCA"&gt;&lt;SPAN class="T286Pc" data-sfc-cp=""&gt;You can then read the HR timestamp value from a dedicated register.&lt;/SPAN&gt;&lt;SPAN class="uJ19be notranslate" data-wiz-uids="Yqxuse_1j,Yqxuse_1k"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/LI&gt;
&lt;/UL&gt;
&lt;/LI&gt;
&lt;/UL&gt;
&lt;/LI&gt;
&lt;/UL&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAQQAA" data-processed="true"&gt;How to enable HR Timestamp&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAQQAA" data-processed="true"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;OL class="VimKh" data-processed="true"&gt;
&lt;LI data-hveid="CAYQAA"&gt;&lt;SPAN class="T286Pc" data-sfc-cp=""&gt;Configure the External Timer (STM): Set up the STM to provide a high-resolution time base.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAYQAQ"&gt;&lt;SPAN class="T286Pc" data-sfc-cp=""&gt;Enable HR Timestamp in FlexCAN: In the FlexCAN controller, enable the HR timestamp feature.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAYQAg"&gt;&lt;SPAN class="T286Pc" data-sfc-cp=""&gt;Read the timestamp&lt;STRONG class="Yjhzub"&gt;:&lt;/STRONG&gt; Read the &lt;CODE class="o8j0Mc"&gt;HR_TIME_STAMP&lt;/CODE&gt; register to get the high-resolution timestamp&lt;/SPAN&gt;&lt;/LI&gt;
&lt;/OL&gt;
&lt;P&gt;&lt;SPAN class="T286Pc" data-sfc-cp=""&gt;Regards&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;LI-WRAPPER&gt;&lt;/LI-WRAPPER&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 02 Oct 2025 13:57:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8mp-flexcan-hardware-timestamp/m-p/2179382#M241116</guid>
      <dc:creator>Bio_TICFSL</dc:creator>
      <dc:date>2025-10-02T13:57:43Z</dc:date>
    </item>
    <item>
      <title>Re: imx8mp flexcan hardware timestamp</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-flexcan-hardware-timestamp/m-p/2179717#M241130</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;Thank you for your response.&lt;BR /&gt;We are aware that the HW Flexcan controller in the imx8mp supports this hardware timestamp feature.&lt;BR /&gt;Could you please confirm whether the Linux driver provided by NXP in kernel 6.6.23 also supports this feature?&lt;/P&gt;&lt;P&gt;Best regards and thank you&lt;/P&gt;&lt;P&gt;Angel&lt;/P&gt;</description>
      <pubDate>Fri, 03 Oct 2025 06:18:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8mp-flexcan-hardware-timestamp/m-p/2179717#M241130</guid>
      <dc:creator>AngelF</dc:creator>
      <dc:date>2025-10-03T06:18:15Z</dc:date>
    </item>
    <item>
      <title>Re: imx8mp flexcan hardware timestamp</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-flexcan-hardware-timestamp/m-p/2179809#M241135</link>
      <description>&lt;UL&gt;&lt;LI&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;Default 16-bit timer:&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN&gt;&amp;nbsp;The FlexCAN module has a built-in 16-bit timer that counts the bit intervals on the CAN bus.&lt;/SPAN&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;SPAN&gt;And has a nasty feature that every time CAN clock synchronization takes place, this 16-bit timer clock period is affected a bit. Not all of this 16-bit timer periods are equal to bit time. So if you try to use some other on-SoC timer (with clock derived from the same clock parent as CAN clock) to count 16-bit timer overflows to extend the width of timestamp clock, you will need to somehow track the drift of timestamp clock due to CAN receive traffic.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 03 Oct 2025 09:02:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8mp-flexcan-hardware-timestamp/m-p/2179809#M241135</guid>
      <dc:creator>kef2</dc:creator>
      <dc:date>2025-10-03T09:02:59Z</dc:date>
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