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    <title>i.MX ProcessorsのトピックRe: iMX8QM cortex m4 UART instance</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX8QM-cortex-m4-UART-instance/m-p/2159506#M240366</link>
    <description>&lt;P&gt;Hi&amp;nbsp;&lt;SPAN class=""&gt;&lt;A href="https://community.nxp.com/t5/user/viewprofilepage/user-id/206761" target="_self"&gt;&lt;SPAN class=""&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/206761"&gt;@Chavira&lt;/a&gt;&lt;/SPAN&gt;&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Thanks for your response.&lt;/P&gt;&lt;P&gt;My original problem was that I wanted to switch the debug console UART on Cortex-M4 core 0 to another UART, because the default pin (M40_UART) used in the SDK &lt;STRONG&gt;hello_world&lt;/STRONG&gt; example is already in use by another core on my board. That’s why I needed to understand what the instance field in &lt;FONT face="courier new,courier"&gt;hal_uart_config_t&lt;/FONT&gt; really meant. In &lt;FONT face="courier new,courier"&gt;DbgConsole_Init()&lt;/FONT&gt; I need to pass that value.&lt;BR /&gt;&lt;BR /&gt;After checking some files related to that function. in MIMX8QM6_cm4_core0.h I found the definitions of the uart base address.&lt;/P&gt;&lt;LI-CODE lang="c"&gt;/** Array initializer of LPUART peripheral base addresses */
#define LPUART_BASE_ADDRS { CM4_0__LPUART_BASE, CM4_1__LPUART_BASE, DMA__LPUART0_BASE, DMA__LPUART1_BASE, DMA__LPUART2_BASE, DMA__LPUART3_BASE, DMA__LPUART4_BASE, SCU__LPUART_BASE }
/** Array initializer of LPUART peripheral base pointers */
#define LPUART_BASE_PTRS { CM4_0__LPUART, CM4_1__LPUART, DMA__LPUART0, DMA__LPUART1, DMA__LPUART2, DMA__LPUART3, DMA__LPUART4, SCU__LPUART }  &lt;/LI-CODE&gt;&lt;P&gt;So the instance field is just the index into this array of base addresses (?). It works anyway. Thanks&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;io&lt;/P&gt;</description>
    <pubDate>Thu, 28 Aug 2025 02:13:23 GMT</pubDate>
    <dc:creator>io</dc:creator>
    <dc:date>2025-08-28T02:13:23Z</dc:date>
    <item>
      <title>iMX8QM cortex m4 UART instance</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX8QM-cortex-m4-UART-instance/m-p/2158281#M240320</link>
      <description>&lt;DIV&gt;Here is board.h definitions I got from sdk example&lt;/DIV&gt;&lt;DIV&gt;#if defined(MIMX8QM_CM4_CORE0&lt;BR /&gt;#define BOARD_DEBUG_UART_BASEADDR (uint32_t) CM4_0__LPUART&lt;BR /&gt;#define BOARD_DEBUG_UART_INSTANCE 0U&lt;BR /&gt;#define BOARD_DEBUG_UART_SC_RSRC SC_R_M4_0_UART&lt;BR /&gt;#define BOARD_DEBUG_UART_CLKSRC kCLOCK_M4_0_Lpuart&lt;BR /&gt;#define BOARD_UART_IRQ M4_0_LPUART_IRQn&lt;BR /&gt;#define BOARD_UART_IRQ_HANDLER M4_0_LPUART_IRQHandler&lt;BR /&gt;#define BOARD_M4_CPU_RSRC SC_R_M4_0_PID0&lt;BR /&gt;#elif defined(MIMX8QM_CM4_CORE1)&lt;BR /&gt;#define BOARD_DEBUG_UART_BASEADDR (uint32_t) DMA__LPUART2&lt;BR /&gt;#define BOARD_DEBUG_UART_INSTANCE 4U&lt;BR /&gt;#define BOARD_DEBUG_UART_SC_RSRC SC_R_UART_2&lt;BR /&gt;#define BOARD_DEBUG_UART_CLKSRC kCLOCK_DMA_Lpuart2&lt;BR /&gt;#define BOARD_UART_IRQ DMA_UART2_INT_IRQn&lt;BR /&gt;#define BOARD_UART_IRQ_HANDLER DMA_UART2_INT_IRQHandler&lt;BR /&gt;#define BOARD_M4_CPU_RSRC SC_R_M4_1_PID0&lt;BR /&gt;#else&lt;BR /&gt;#error "No valid BOARD_DEBUG_UART_BASEADDR defined."&lt;BR /&gt;#endif&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;And this is a struct contains uart instance that needed to specify in function DbgConsole_Init()&lt;BR /&gt;/*! @brief UART configuration structure. */&lt;BR /&gt;typedef struct _hal_uart_config&lt;BR /&gt;{&lt;BR /&gt;uint32_t srcClock_Hz; /*!&amp;lt; Source clock */&lt;BR /&gt;uint32_t baudRate_Bps; /*!&amp;lt; Baud rate */&lt;BR /&gt;hal_uart_parity_mode_t parityMode; /*!&amp;lt; Parity mode, disabled (default), even, odd */&lt;BR /&gt;hal_uart_stop_bit_count_t stopBitCount; /*!&amp;lt; Number of stop bits, 1 stop bit (default) or 2 stop bits */&lt;BR /&gt;uint8_t enableRx; /*!&amp;lt; Enable RX */&lt;BR /&gt;uint8_t enableTx; /*!&amp;lt; Enable TX */&lt;BR /&gt;uint8_t enableRxRTS; /*!&amp;lt; Enable RX RTS */&lt;BR /&gt;uint8_t enableTxCTS; /*!&amp;lt; Enable TX CTS */&lt;BR /&gt;uint8_t instance; /*!&amp;lt; Instance (0 - UART0, 1 - UART1, ...), detail information please refer to the&lt;BR /&gt;SOC corresponding RM.&lt;BR /&gt;Invalid instance value will cause initialization failure. */&lt;BR /&gt;#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) &amp;amp;&amp;amp; (UART_ADAPTER_NON_BLOCKING_MODE &amp;gt; 0U))&lt;BR /&gt;hal_uart_block_mode_t mode; /*!&amp;lt; Uart block mode */&lt;BR /&gt;#endif /* UART_ADAPTER_NON_BLOCKING_MODE */&lt;BR /&gt;#if (defined(HAL_UART_ADAPTER_FIFO) &amp;amp;&amp;amp; (HAL_UART_ADAPTER_FIFO &amp;gt; 0u))&lt;BR /&gt;uint8_t txFifoWatermark;&lt;BR /&gt;uint8_t rxFifoWatermark;&lt;BR /&gt;#endif&lt;BR /&gt;} hal_uart_config_t;&lt;BR /&gt;&lt;BR /&gt;Could you explain me what is uart instance? Where can I find information about uart instance? I know the comments said its in SoC Ref. Manual but I still can't figure out which one?&lt;/DIV&gt;</description>
      <pubDate>Tue, 26 Aug 2025 11:07:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX8QM-cortex-m4-UART-instance/m-p/2158281#M240320</guid>
      <dc:creator>io</dc:creator>
      <dc:date>2025-08-26T11:07:21Z</dc:date>
    </item>
    <item>
      <title>Re: iMX8QM cortex m4 UART instance</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX8QM-cortex-m4-UART-instance/m-p/2158387#M240325</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/254087"&gt;@io&lt;/a&gt;!&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;In the context of embedded systems and SDKs like the one you're using, a UART instance refers to a specific UART peripheral available on your SoC (System on Chip). Most modern SoCs have multiple UARTs (e.g., UART0, UART1, UART2, etc.), and each one is assigned an instance number.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;or your case, since you're working with the NXP i.MX8QM, here’s how to locate the UART instance:&lt;/P&gt;
&lt;P&gt;Open the i.MX8QM Reference Manual.&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;Search for LPUART or UART in the document.&lt;BR /&gt;Look for a section like Peripheral Memory Map or UART Overview.&lt;BR /&gt;Each UART peripheral (e.g., LPUART0, LPUART1, etc.) will be listed with:&lt;BR /&gt;Its base address&lt;BR /&gt;Its instance number&lt;BR /&gt;Its interrupt vector&lt;BR /&gt;Its clock source&lt;BR /&gt;&lt;BR /&gt;Best Regards,&lt;/P&gt;
&lt;P&gt;Chvaira&lt;/P&gt;</description>
      <pubDate>Tue, 26 Aug 2025 14:00:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX8QM-cortex-m4-UART-instance/m-p/2158387#M240325</guid>
      <dc:creator>Chavira</dc:creator>
      <dc:date>2025-08-26T14:00:15Z</dc:date>
    </item>
    <item>
      <title>Re: iMX8QM cortex m4 UART instance</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX8QM-cortex-m4-UART-instance/m-p/2159506#M240366</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;SPAN class=""&gt;&lt;A href="https://community.nxp.com/t5/user/viewprofilepage/user-id/206761" target="_self"&gt;&lt;SPAN class=""&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/206761"&gt;@Chavira&lt;/a&gt;&lt;/SPAN&gt;&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Thanks for your response.&lt;/P&gt;&lt;P&gt;My original problem was that I wanted to switch the debug console UART on Cortex-M4 core 0 to another UART, because the default pin (M40_UART) used in the SDK &lt;STRONG&gt;hello_world&lt;/STRONG&gt; example is already in use by another core on my board. That’s why I needed to understand what the instance field in &lt;FONT face="courier new,courier"&gt;hal_uart_config_t&lt;/FONT&gt; really meant. In &lt;FONT face="courier new,courier"&gt;DbgConsole_Init()&lt;/FONT&gt; I need to pass that value.&lt;BR /&gt;&lt;BR /&gt;After checking some files related to that function. in MIMX8QM6_cm4_core0.h I found the definitions of the uart base address.&lt;/P&gt;&lt;LI-CODE lang="c"&gt;/** Array initializer of LPUART peripheral base addresses */
#define LPUART_BASE_ADDRS { CM4_0__LPUART_BASE, CM4_1__LPUART_BASE, DMA__LPUART0_BASE, DMA__LPUART1_BASE, DMA__LPUART2_BASE, DMA__LPUART3_BASE, DMA__LPUART4_BASE, SCU__LPUART_BASE }
/** Array initializer of LPUART peripheral base pointers */
#define LPUART_BASE_PTRS { CM4_0__LPUART, CM4_1__LPUART, DMA__LPUART0, DMA__LPUART1, DMA__LPUART2, DMA__LPUART3, DMA__LPUART4, SCU__LPUART }  &lt;/LI-CODE&gt;&lt;P&gt;So the instance field is just the index into this array of base addresses (?). It works anyway. Thanks&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;io&lt;/P&gt;</description>
      <pubDate>Thu, 28 Aug 2025 02:13:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX8QM-cortex-m4-UART-instance/m-p/2159506#M240366</guid>
      <dc:creator>io</dc:creator>
      <dc:date>2025-08-28T02:13:23Z</dc:date>
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