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    <title>topic Re: Quad SPI availability with iMX6 in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Quad-SPI-availability-with-iMX6/m-p/254475#M24029</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The current i.MX6 products (6Quad, 6Dual, 6DualLite, 6Solo and 6SoloLite) do not support QSPI. This appears to be an error in the presentation.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Clay&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 09 Sep 2013 15:14:51 GMT</pubDate>
    <dc:creator>Clay_Turner</dc:creator>
    <dc:date>2013-09-09T15:14:51Z</dc:date>
    <item>
      <title>Quad SPI availability with iMX6</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Quad-SPI-availability-with-iMX6/m-p/254473#M24027</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I would like to know if there is any possibility to have a Quad SPI (or QSPI) interface with an iMX6Solo in order to have a faster access to SPI NOR.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The datasheet offers 2 single data standard SPI interface with 4 chip select pins,&lt;/P&gt;&lt;P&gt;and several SDIO interfaces with 4 to&lt;SPAN style="font-family: arial,helvetica,sans-serif; font-size: 10pt;"&gt; 8 bits data bus width.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: arial,helvetica,sans-serif; font-size: 10pt;"&gt;In the &lt;SPAN style="color: #685c53; font-weight: bold;"&gt;SABRE Platform for IPTV based on i.MX 6&amp;nbsp; &lt;/SPAN&gt;&lt;SPAN style="color: #685c53; font-weight: bold;"&gt;Block Diagram&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;2 QSPI are mentionned but nothing else.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Does anyone could confirm if it is possible to have a Quad SPI interface ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanls for your help,&lt;/P&gt;&lt;P&gt;Regards.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Pousssemousse&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 04 Jul 2013 09:55:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Quad-SPI-availability-with-iMX6/m-p/254473#M24027</guid>
      <dc:creator>Poussemousse</dc:creator>
      <dc:date>2013-07-04T09:55:06Z</dc:date>
    </item>
    <item>
      <title>Re: Quad SPI availability with iMX6</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Quad-SPI-availability-with-iMX6/m-p/254474#M24028</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;As per described in the mx6 solo reference manual, it contains the standard ECSPI block.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 05 Sep 2013 17:21:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Quad-SPI-availability-with-iMX6/m-p/254474#M24028</guid>
      <dc:creator>fabio_estevam</dc:creator>
      <dc:date>2013-09-05T17:21:59Z</dc:date>
    </item>
    <item>
      <title>Re: Quad SPI availability with iMX6</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Quad-SPI-availability-with-iMX6/m-p/254475#M24029</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The current i.MX6 products (6Quad, 6Dual, 6DualLite, 6Solo and 6SoloLite) do not support QSPI. This appears to be an error in the presentation.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Clay&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 09 Sep 2013 15:14:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Quad-SPI-availability-with-iMX6/m-p/254475#M24029</guid>
      <dc:creator>Clay_Turner</dc:creator>
      <dc:date>2013-09-09T15:14:51Z</dc:date>
    </item>
    <item>
      <title>Re: Quad SPI availability with iMX6</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Quad-SPI-availability-with-iMX6/m-p/254476#M24030</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Bruce or Clay ??&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for this clarification. Do you expect to have a future firmware revision with Quad SPI integrated in the chip ?&lt;/P&gt;&lt;P&gt;Starting from &lt;SPAN style="font-size: 11.0pt; font-family: 'Arial','sans-serif';"&gt;USDHC&lt;/SPAN&gt; peripheral should not be too complicated to offer a Quad SPI bus to your customers.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Poussemousse.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 09 Sep 2013 15:25:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Quad-SPI-availability-with-iMX6/m-p/254476#M24030</guid>
      <dc:creator>Poussemousse</dc:creator>
      <dc:date>2013-09-09T15:25:08Z</dc:date>
    </item>
    <item>
      <title>Re: Quad SPI availability with iMX6</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Quad-SPI-availability-with-iMX6/m-p/254477#M24031</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes. A future chip will have a dedicated Quad SPI peripheral (implemented in hardware not in firmware through another interface).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Clay&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 09 Sep 2013 16:11:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Quad-SPI-availability-with-iMX6/m-p/254477#M24031</guid>
      <dc:creator>Clay_Turner</dc:creator>
      <dc:date>2013-09-09T16:11:55Z</dc:date>
    </item>
    <item>
      <title>Re: Quad SPI availability with iMX6</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Quad-SPI-availability-with-iMX6/m-p/254478#M24032</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Will this chip be pin to pin compatible with current iMX6,&lt;/P&gt;&lt;P&gt;and when do you expect to propose such component ?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 10 Sep 2013 06:40:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Quad-SPI-availability-with-iMX6/m-p/254478#M24032</guid>
      <dc:creator>Poussemousse</dc:creator>
      <dc:date>2013-09-10T06:40:41Z</dc:date>
    </item>
    <item>
      <title>Re: Quad SPI availability with iMX6</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Quad-SPI-availability-with-iMX6/m-p/254479#M24033</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Unfortunately, I can't provide details about unannounced products.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Clay&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 10 Sep 2013 22:37:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Quad-SPI-availability-with-iMX6/m-p/254479#M24033</guid>
      <dc:creator>Clay_Turner</dc:creator>
      <dc:date>2013-09-10T22:37:07Z</dc:date>
    </item>
    <item>
      <title>Re: Quad SPI availability with iMX6</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Quad-SPI-availability-with-iMX6/m-p/254480#M24034</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Vybrid is an announced Freescale product that supports QuadSPI.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Driver has alreadby been submitted:&lt;/P&gt;&lt;P&gt;&lt;A href="http://www.spinics.net/lists/linux-doc/msg14255.html" title="http://www.spinics.net/lists/linux-doc/msg14255.html"&gt;[PATCH v3 0/8] Add the Quadspi driver for vf610-twr (Linux Doc)&lt;/A&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 10 Sep 2013 23:02:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Quad-SPI-availability-with-iMX6/m-p/254480#M24034</guid>
      <dc:creator>fabio_estevam</dc:creator>
      <dc:date>2013-09-10T23:02:11Z</dc:date>
    </item>
    <item>
      <title>Re: Quad SPI availability with iMX6</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Quad-SPI-availability-with-iMX6/m-p/254481#M24035</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;According Freescale news :&lt;/P&gt;&lt;P&gt;&lt;A href="http://media.freescale.com/phoenix.zhtml?c=196520&amp;amp;p=irol-newsArticle&amp;amp;ID=1917475&amp;amp;highlight="&gt;http://media.freescale.com/phoenix.zhtml?c=196520&amp;amp;p=irol-newsArticle&amp;amp;ID=1917475&amp;amp;highlight=&lt;/A&gt;&lt;/P&gt;&lt;P&gt;iMX6SoloX will provide the feature plus :&lt;/P&gt;&lt;P&gt;&lt;EM&gt; Additional features of the newest i.MX 6 series processor include: &lt;/EM&gt;&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;&lt;EM&gt; Dual-port gigabit Ethernet audio video bridging (AVB) for quality-of-service in automotive and other applications with enhanced traffic shaping and packet prioritization. &lt;/EM&gt;&lt;/LI&gt;&lt;LI&gt;&lt;EM&gt; Cost-effective 2D and 3D graphics processing unit (GPU) for enhanced HMI development. &lt;/EM&gt;&lt;/LI&gt;&lt;LI&gt;&lt;EM&gt; Flexible boot options, including support for quad SPI and raw NAND, and a memory controller that interfaces to both DDR3 and low power DDR2. &lt;/EM&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 06 Jun 2014 06:38:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Quad-SPI-availability-with-iMX6/m-p/254481#M24035</guid>
      <dc:creator>Poussemousse</dc:creator>
      <dc:date>2014-06-06T06:38:47Z</dc:date>
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