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    <title>i.MX Processors中的主题 Re: i.MX 8M Plus: SDMA Memory to Memory Performance</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-8M-Plus-SDMA-Memory-to-Memory-Performance/m-p/2154083#M240180</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;thank you for the fast reply, but it does not answer my question.&lt;/P&gt;&lt;P&gt;I know that it is possible to copy from one memory location to another memory location using the current SDMA API. But the question was:&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;Why is the performance of the SDMA so slow: 124MB/s?&lt;/LI&gt;&lt;LI&gt;And is there a way to increase the throughput?&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;BR&lt;/P&gt;</description>
    <pubDate>Tue, 19 Aug 2025 06:23:55 GMT</pubDate>
    <dc:creator>stollg</dc:creator>
    <dc:date>2025-08-19T06:23:55Z</dc:date>
    <item>
      <title>i.MX 8M Plus: SDMA Memory to Memory Performance</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-8M-Plus-SDMA-Memory-to-Memory-Performance/m-p/2149269#M239990</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;We are currently developing an application where we have to copy 16384Bytes of data from shared memory (protected by a Messaging Unit)&amp;nbsp; to "normal" memory. The copy process is executed by the M7 co-processor at 800MHz an takes:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;~150us on a non-cacheable memory area (110MB/s)&lt;/LI&gt;&lt;LI&gt;~90us on a cacheable memory area (190MB/s)&lt;/LI&gt;&lt;LI&gt;~50-90us when using stack memory (200-400MB/s)&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;Since we are working on shared-memory, we are talking about non-cacheable memory and therefore it takes 150us. To make the process faster, we tried to use the Memory to Memory function of the Smart Direct Memory Access Controller (SDMA). But also with that one:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;133us on non-cacheable memory area (124MB/s)&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;This is a little bit faster, but still not really faster than the standard memcpy on the M7 processor. At 800MHz on the SDMA this would also mean, that it takes at least 7 instructions per byte. Or if we assume that the SDMA uses 32bit transfer, we would talk about 29 instructions per transfer.&lt;BR /&gt;All the memory areas are aligned at 32Bytes. Is there anything else which can be done to increase the SDMAs performance?&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Used code:&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;sdma_handle_t&lt;/SPAN&gt; &lt;SPAN&gt;g_SDMA_Handle&lt;/SPAN&gt;&lt;SPAN&gt; = {&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;};&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;volatile&lt;/SPAN&gt; &lt;SPAN&gt;bool&lt;/SPAN&gt; &lt;SPAN&gt;g_Transfer_Done&lt;/SPAN&gt;&lt;SPAN&gt; = &lt;/SPAN&gt;&lt;SPAN&gt;false&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;AT_NONCACHEABLE_SECTION_ALIGN&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;sdma_context_data_t&lt;/SPAN&gt;&lt;SPAN&gt; context, &lt;/SPAN&gt;&lt;SPAN&gt;4&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;AT_NONCACHEABLE_SECTION_ALIGN&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;uint32_t&lt;/SPAN&gt; &lt;SPAN&gt;srcAddr&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;BUFF_LENGTH&lt;/SPAN&gt;&lt;SPAN&gt;], &lt;/SPAN&gt;&lt;SPAN&gt;32&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;AT_NONCACHEABLE_SECTION_ALIGN&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;uint32_t&lt;/SPAN&gt; &lt;SPAN&gt;destAddr&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;BUFF_LENGTH&lt;/SPAN&gt;&lt;SPAN&gt;], &lt;/SPAN&gt;&lt;SPAN&gt;32&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;int&lt;/SPAN&gt; &lt;SPAN&gt;main&lt;/SPAN&gt;&lt;SPAN&gt;() {&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;...&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;SDMA_GetDefaultConfig&lt;/SPAN&gt;&lt;SPAN&gt;(&amp;amp;userConfig);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;userConfig&lt;/SPAN&gt;&lt;SPAN&gt;.&lt;/SPAN&gt;&lt;SPAN&gt;ratio&lt;/SPAN&gt;&lt;SPAN&gt; = kSDMA_ARMClockFreq;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;SDMA_Init&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;EXAMPLE_SDMAARM&lt;/SPAN&gt;&lt;SPAN&gt;, &amp;amp;userConfig);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;SDMA_CreateHandle&lt;/SPAN&gt;&lt;SPAN&gt;(&amp;amp;g_SDMA_Handle, &lt;/SPAN&gt;&lt;SPAN&gt;EXAMPLE_SDMAARM&lt;/SPAN&gt;&lt;SPAN&gt;, &lt;/SPAN&gt;&lt;SPAN&gt;1&lt;/SPAN&gt;&lt;SPAN&gt;, &amp;amp;context);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;SDMA_SetCallback&lt;/SPAN&gt;&lt;SPAN&gt;(&amp;amp;g_SDMA_Handle, SDMA_Callback, &lt;/SPAN&gt;&lt;SPAN&gt;NULL&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;SDMA_PrepareTransfer&lt;/SPAN&gt;&lt;SPAN&gt;(&amp;amp;transferConfig, (&lt;/SPAN&gt;&lt;SPAN&gt;uint32_t&lt;/SPAN&gt;&lt;SPAN&gt;)srcAddr, (&lt;/SPAN&gt;&lt;SPAN&gt;uint32_t&lt;/SPAN&gt;&lt;SPAN&gt;)destAddr, &lt;/SPAN&gt;&lt;SPAN&gt;sizeof&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;srcAddr&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;]), &lt;/SPAN&gt;&lt;SPAN&gt;sizeof&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;destAddr&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;]),&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;sizeof&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;srcAddr&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;]), &lt;/SPAN&gt;&lt;SPAN&gt;sizeof&lt;/SPAN&gt;&lt;SPAN&gt;(srcAddr), &lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;, kSDMA_PeripheralTypeMemory, kSDMA_MemoryToMemory );&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;SDMA_SubmitTransfer&lt;/SPAN&gt;&lt;SPAN&gt;(&amp;amp;g_SDMA_Handle, &amp;amp;transferConfig);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;SDMA_SetChannelPriority&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;EXAMPLE_SDMAARM&lt;/SPAN&gt;&lt;SPAN&gt;, &lt;/SPAN&gt;&lt;SPAN&gt;1&lt;/SPAN&gt;&lt;SPAN&gt;, &lt;/SPAN&gt;&lt;SPAN&gt;2U&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;g_Transfer_Done = &lt;/SPAN&gt;&lt;SPAN&gt;false&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;uint32_t&lt;/SPAN&gt;&lt;SPAN&gt; tStart = &lt;/SPAN&gt;&lt;SPAN&gt;timerGetMicroSeconds&lt;/SPAN&gt;&lt;SPAN&gt;();&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;SDMA_StartTransfer&lt;/SPAN&gt;&lt;SPAN&gt;(&amp;amp;g_SDMA_Handle);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;while&lt;/SPAN&gt;&lt;SPAN&gt; (g_Transfer_Done != &lt;/SPAN&gt;&lt;SPAN&gt;true&lt;/SPAN&gt;&lt;SPAN&gt;){ }&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;int32_t&lt;/SPAN&gt;&lt;SPAN&gt; timerDiff = &lt;/SPAN&gt;&lt;SPAN&gt;timerDiffMicroSeconds&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;timerGetMicroSeconds&lt;/SPAN&gt;&lt;SPAN&gt;(), tStart);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;...&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;P&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 08 Aug 2025 14:15:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-8M-Plus-SDMA-Memory-to-Memory-Performance/m-p/2149269#M239990</guid>
      <dc:creator>stollg</dc:creator>
      <dc:date>2025-08-08T14:15:44Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX 8M Plus: SDMA Memory to Memory Performance</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-8M-Plus-SDMA-Memory-to-Memory-Performance/m-p/2150148#M240030</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;Not possible, copy ram to ram, with current SDMA API.&lt;/P&gt;
&lt;P&gt;Regards&lt;/P&gt;</description>
      <pubDate>Mon, 11 Aug 2025 14:07:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-8M-Plus-SDMA-Memory-to-Memory-Performance/m-p/2150148#M240030</guid>
      <dc:creator>Bio_TICFSL</dc:creator>
      <dc:date>2025-08-11T14:07:50Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX 8M Plus: SDMA Memory to Memory Performance</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-8M-Plus-SDMA-Memory-to-Memory-Performance/m-p/2153337#M240152</link>
      <description>&lt;P&gt;Sorry, but I can not accepts this answer, since the copy from ram to ram is possible with the code snipped provided in the original answer.&lt;BR /&gt;It uses the SDMA script located at SDMA address 644:&lt;BR /&gt;&amp;nbsp;&amp;nbsp; #define FSL_SDMA_M2M_ADDR 644&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; sdma_transfer_type_t is kSDMA_MemoryToMemory&lt;BR /&gt;&lt;BR /&gt;But the problem is, that it is not faster compared to a standard memcpy on the M7-core.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;In the datasheet there is also a dedicated section which describes a fast ram to ram copy:&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; 7.2.3.12.1.9 Burst DMA Unit Copy Mode.&lt;BR /&gt;&lt;BR /&gt;So, how can we use this feature?&lt;/P&gt;&lt;P&gt;BR&lt;/P&gt;</description>
      <pubDate>Mon, 18 Aug 2025 06:46:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-8M-Plus-SDMA-Memory-to-Memory-Performance/m-p/2153337#M240152</guid>
      <dc:creator>stollg</dc:creator>
      <dc:date>2025-08-18T06:46:12Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX 8M Plus: SDMA Memory to Memory Performance</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-8M-Plus-SDMA-Memory-to-Memory-Performance/m-p/2153699#M240163</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;You are copy from M7 to cortex or viceversa that;s possible. but copy from the same source is not possible in the current SDMA API.&lt;/P&gt;
&lt;P&gt;Regards&lt;/P&gt;</description>
      <pubDate>Mon, 18 Aug 2025 14:03:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-8M-Plus-SDMA-Memory-to-Memory-Performance/m-p/2153699#M240163</guid>
      <dc:creator>Bio_TICFSL</dc:creator>
      <dc:date>2025-08-18T14:03:22Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX 8M Plus: SDMA Memory to Memory Performance</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-8M-Plus-SDMA-Memory-to-Memory-Performance/m-p/2154083#M240180</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;thank you for the fast reply, but it does not answer my question.&lt;/P&gt;&lt;P&gt;I know that it is possible to copy from one memory location to another memory location using the current SDMA API. But the question was:&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;Why is the performance of the SDMA so slow: 124MB/s?&lt;/LI&gt;&lt;LI&gt;And is there a way to increase the throughput?&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;BR&lt;/P&gt;</description>
      <pubDate>Tue, 19 Aug 2025 06:23:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-8M-Plus-SDMA-Memory-to-Memory-Performance/m-p/2154083#M240180</guid>
      <dc:creator>stollg</dc:creator>
      <dc:date>2025-08-19T06:23:55Z</dc:date>
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