topic Re: iMX8QM and LPDDR4 memory errors in i.MX Processors

iMX8QM and LPDDR4 memory errors

emanuele_tdx — Wed, 18 Jun 2025 14:51:31 GMT

Hello,
We are introducing the Nanya NT6AN512T32AV-J1I (https://www.nanya.com/en/Product/4404/NT6AN512T32AV-J1I) memory on our Apalis iMX8 (i.MX8QM) module as a replacement for the Micron MT53D512M32D2DS-046 IT:D (mt53d512m32d2ds-046-ait-d )

We have reviewed the timing specifications, and the Nanya part appears to be a drop-in replacement for the Micron one, as both seem to have the same timing requirements.

We tested several modules equipped with the Nanya memory using the same test setup as for the Micron version (Linux BSP + Memtester [memtester-4.6.0.tar.gz To be sure we have also re-run the test on the Micron modules.

The Nanya memory performs well at different temperature ranges, but in the higher range (~50°C to ~80°C), during the Bit Spread (but not only) test in Memtester, we observed the following failures (these are a subset of the total failures we had):

FAILURE: 0xffffffffffffffff != 0xfffffffffbffffff at offset 0x00000000031a9a80.
FAILURE: 0xffffffffffffffff != 0xfffffffffbffffff at offset 0x0000000009eb5440.
FAILURE: 0xffffffffffffffff != 0xfffffffffbffffff at offset 0x000000000172b040.
FAILURE: 0xfffffffffbffffff != 0xffffffffffffffff at offset 0x000000000792e570.
FAILURE: 0xffffffffffffffff != 0xfffffffffbffffff at offset 0x000000000a13fb00.

It is important to note that these errors appear only when we start testing at -40°C and ramp up to 85°C without rebooting. If we start the test at 85°C and ramp down to -40°C, we do not observe any errors. Due to this, we suspect that LPDDR4 training at -40 is affecting the reliability of the memory (maybe there are signal integrity issues when training is done at -40 degrees).

We also dumped some DDR controller registers related to memory training, and we noticed significant differences between the two memory types (see attachments). We suspect that some termination or drive strength parameters may need to be tuned for the Nanya memory, but we are not sure which ones.

We have also attached the RPA (Register Programming Aid) Excel sheet containing the DDR controller configuration currently used for both memory types.

Any advice or suggestions are welcome, but specifically, we have the following questions:

Can the comparison of the training result registers help identify the root cause or highlight key differences between the two memory types?
Have you any suggestion around memory configuration to improve training and signal integrity?

Thank you in advance for your support.

Re: iMX8QM and LPDDR4 memory errors

pengyong_zhang — Thu, 19 Jun 2025 02:58:40 GMT

Hi @emanuele_tdx

Did you try use the Micron DRAM run the same test see if this error log will occurred too?

B.R

Re: iMX8QM and LPDDR4 memory errors

emanuele_tdx — Thu, 19 Jun 2025 05:25:38 GMT

Hi @pengyong_zhang,

Yes, we did. It works without any error.

Emanuele

Re: iMX8QM and LPDDR4 memory errors

pengyong_zhang — Thu, 19 Jun 2025 06:37:54 GMT

Hi @emanuele_tdx

Then, i think you should ask the Nanya's vendor talk about this error. Ask if their DDR can pass this test at your test Scenario. It has nothing to do with DDR training.

B.R

Re: iMX8QM and LPDDR4 memory errors

emanuele_tdx — Thu, 19 Jun 2025 06:41:54 GMT

Hi,
already done. They expect the memory to work in these conditions.
I'm asking here to understand if we can tune the configuration to be able to fix these errors: termination, drive strength, latencies, and, in general, timings.
Regards,
Emanuele

Re: iMX8QM and LPDDR4 memory errors

pengyong_zhang — Fri, 20 Jun 2025 05:33:41 GMT

Hi @emanuele_tdx

Got your information, You can use our MX8QM_B0_LPDDR4_RPA_1.6GHz_v23.xlsx file choose different DS value then re-run the test see if this error can be solved. Because your error was occurred when the environment temperature from low to high. i suggest you can try the DS from 40->48. And see the test result.

B.R

Re: iMX8QM and LPDDR4 memory errors

emanuele_tdx — Fri, 20 Jun 2025 11:10:58 GMT

Hi @pengyong_zhang,

thank you for the hint.

We have already done a test by setting both ZPROG_DRAM_ODT and ZPROG_ASYM_PD_DRV in RPA from 40 to 48 - Register DDR_PHY_ZQ1PR0 (DQ bus impedance Control) (and also from 40 to 34) without any difference.

Let me know your opinion about testing only ZPROG_ASYM_PD_DRV to 48 (or maybe a higher value).

Regards,

Emanuele

Re: iMX8QM and LPDDR4 memory errors

pengyong_zhang — Mon, 23 Jun 2025 08:33:43 GMT

Hi @emanuele_tdx

Actually, i am not make sure which DS value or ODT value will resolve this problem.

But there is another method you can try:

Modify the MR12 value through SCFW imx8qm_dcd_1.6GHz.cfg file, refer the below code.

DATA 4 DDR_PHY_MR12_0 0x48

Adjust the test from 25.2% down. Test in sequence.

B.R

Re: iMX8QM and LPDDR4 memory errors

hongting_dong — Tue, 24 Jun 2025 01:35:56 GMT

Hi @emanuele_tdx

Please also update info:

Nanya Failing device info :

MFD Date code:

LOT number is :

And have you tried Nanya's latest device part, from my remember, their device parts have some updates in ZQ cal

Best Regards

Re: iMX8QM and LPDDR4 memory errors

emanuele_tdx — Tue, 24 Jun 2025 10:32:29 GMT

Hi @pengyong_zhang ,

You proposed to change MR12, do I also have to change MR14?

Sorry, I have another doubt. When you say "test from 25.2% down", do you mean 24.8, 24.4, 24 and so on, or the other way around (25.6, 26, 26.6 and so on)?

Thank you,
kind regards.

Emanuele

Re: iMX8QM and LPDDR4 memory errors

emanuele_tdx — Tue, 24 Jun 2025 15:30:22 GMT

Hello,
on the memory there is written:

Nanya2447

NT6AN512T32AV-J1I

9423W1EF 3 TW

Let me know if this is the information you need.
Thanks!

Regards,
Emanuele

Re: iMX8QM and LPDDR4 memory errors

pengyong_zhang — Wed, 25 Jun 2025 02:00:38 GMT

Hi @emanuele_tdx

Yes, I mean 24.8, 24.4, 24 and so on.

B.R

Re: iMX8QM and LPDDR4 memory errors

emanuele_tdx — Wed, 25 Jun 2025 12:59:38 GMT

Hello @pengyong_zhang,

tested your proposal and also 40 -> 60.

Both tests failed on 7 boards without any significant change (improvement or worsening).

Re: iMX8QM and LPDDR4 memory errors

emanuele_tdx — Wed, 25 Jun 2025 13:03:27 GMT

Hello @pengyong_zhang , @hongting_dong ,

can you focus particularly on this fact:

> It is important to note that these errors appear only when we start testing at -40°C and ramp up to 85°C without rebooting.

As a workaround, can we retrigger memory training on a working system by patching the scfw?
Given the kind of errors we reported (bit flip) is there any trained "parameter" which can help us identify the root problem?

Thank you in advance,
kind regards.

Emanuele

Re: iMX8QM and LPDDR4 memory errors

pengyong_zhang — Thu, 26 Jun 2025 01:49:31 GMT

Hi @emanuele_tdx

Did you run the test about change MR12 register change? What is the test result. And when you run this test, do not change any parameter except MR12.

B.R

Re: iMX8QM and LPDDR4 memory errors

emanuele_tdx — Fri, 27 Jun 2025 10:39:46 GMT

Hello @pengyong_zhang,

I have tested MR12 only change from 0x47 to 0x40.

As well as ZPROG_ASYM_PD_DRV_DQ_48 and ZPROG_ASYM_PD_DRV_DQ_60.

Every configuration failed.
I'm not really able to understand if any of these test was better or worse.

Kind regards,
Emanuele

Re: iMX8QM and LPDDR4 memory errors

pengyong_zhang — Mon, 30 Jun 2025 00:52:58 GMT

Hi @emanuele_tdx

Keep the ZPROG_ASYM_PD_DRV_DQ_48 and ZPROG_ASYM_PD_DRV_DQ_60 as default value. Do not change it.

Then gradually test different MR12 values. Sorry, i can not reproduce your problem, because i do not gave your test board and environment. So you need to test it for your self, and find the right Vref value. Also i think the best way is still ask to Nanya talk about this problem, see if them can reproduce your problem and give you the workaround.

B.R

Re: iMX8QM and LPDDR4 memory errors

emanuele_tdx — Tue, 29 Jul 2025 09:53:43 GMT

Hello @pengyong_zhang , @hongting_dong ,

Nanya analyzed the behaviour and this is their conclusion:

Based on LA MRS setting confirmation, MR18/MR19 were disabled during memory test.
NTC suggest enabling MR18/MR19 on the platform because if the platform does not perform tDQS2DQ offset, the default settings may not meet NTC devices' requirements.

I couldn’t find any setting or information related to the MR18/MR19 registers in the RPA, SCFW, or the i.MX8QM Reference Manual.

Since these are read-only registers on the RAM side, my understanding is that the memory controller or the SCFW should read and use them somewhere at runtime.

Could you help me identify how we might proceed?

Emanuele

Re: iMX8QM and LPDDR4 memory errors

pengyong_zhang — Thu, 31 Jul 2025 08:33:05 GMT

Hi @emanuele_tdx

Nanya means that this error is caused by the board not having regular DQS2DQ training during operation?

B.R

Re: iMX8QM and LPDDR4 memory errors

emanuele_tdx — Thu, 31 Jul 2025 08:35:35 GMT

Hi @pengyong_zhang ,

yes, it is.

Emanuele