imx6ul LCDif controller stop working after reboot

mhe — Tue, 05 Aug 2025 10:46:09 GMT

After about 100 cycles of power on/off or reboot, the LCD controller stops working after boot.

ALL 24 RGB data signals keeps low and CLK，LCD_ENABLE signal keeps high. But others controller like usb or ethernet work well, only the display system corrupts. We try to write new buffer to fb0 device, it does not help. I check the system pixel clock set, it is already enabled by software to nearly 37M which is the LCD panel working frequency.

The issue could be recovered by a new power on/off or system reboot.

The kernel is 4.14.213, we use mxsfb.c lcd driver

pixel clock is enabled as below:

pll3_pfd1_540m 1 1 332307692 0 0

lcdif_pre_sel 1 1 332307692 0 0

lcdif_pred 1 1 110769231 0 0

lcdif_podf 1 1 36923077 0 0

lcdif_pix 1 1 36923077 0 0

iomuxc 0 0 36923077 0 0

lcdif_sel 0 0 36923077 0 0

I dumped all the LCD interface registers as below: The abnormal thing I found is that the register LCDIF_CUR_BUF is all zero, but LCDIF_NEXT_BUF has data. And the (LCDIF_STAT) register shows TXFIFO is empty but also full(confusing)

Memory mapped at address 0xb6f71000.
Read at address 0x021C8000 (0xb6f71000): 0x000A0F21
0x021C8004: /dev/mem opened.
Memory mapped at address 0xb6fbb000.
Read at address 0x021C8010 (0xb6fbb010): 0x00070000
0x021C8020: /dev/mem opened.
Memory mapped at address 0xb6f0b000.
Read at address 0x021C8020 (0xb6f0b020): 0x00200000
0x021C8030: /dev/mem opened.
Memory mapped at address 0xb6f4b000.
Read at address 0x021C8030 (0xb6f4b030): 0x01E00320
0x021C8040: /dev/mem opened.
Memory mapped at address 0xb6fef000.
Read at address 0x021C8040 (0xb6fef040): 0x00000000
0x021C8050: /dev/mem opened.
Memory mapped at address 0xb6fe1000.
Read at address 0x021C8050 (0xb6fe1050): 0x96100000
0x021C8060: /dev/mem opened.
Memory mapped at address 0xb6f70000.
Read at address 0x021C8060 (0xb6f70060): 0x00000000
0x021C8070: /dev/mem opened.
Memory mapped at address 0xb6f72000.
Read at address 0x021C8070 (0xb6f72070): 0x1130000A
0x021C8080: /dev/mem opened.
Memory mapped at address 0xb6f7f000.
Read at address 0x021C8080 (0xb6f7f080): 0x0000020D
0x021C8090: /dev/mem opened.
Memory mapped at address 0xb6fe9000.
Read at address 0x021C8090 (0xb6fe9090): 0x01900496
0x021C80A0: /dev/mem opened.
Memory mapped at address 0xb6f01000.
Read at address 0x021C80A0 (0xb6f010a0): 0x00DC0019
0x021C80B0: /dev/mem opened.
Memory mapped at address 0xb6f45000.
Read at address 0x021C80B0 (0xb6f450b0): 0x00040320
0x021C80C0: /dev/mem opened.
Memory mapped at address 0xb6f37000.
Read at address 0x021C80C0 (0xb6f370c0): 0x00000000
0x021C80D0: /dev/mem opened.
Memory mapped at address 0xb6f88000.
Read at address 0x021C80D0 (0xb6f880d0): 0x00000000
0x021C80E0: /dev/mem opened.
Memory mapped at address 0xb6fc3000.
Read at address 0x021C80E0 (0xb6fc30e0): 0x00000000

0x021C80F0: /dev/mem opened.
Memory mapped at address 0xb6fd2000.
Read at address 0x021C80F0 (0xb6fd20f0): 0x00000000

0x021C8100: /dev/mem opened.
Memory mapped at address 0xb6f49000.
Read at address 0x021C8100 (0xb6f49100): 0x00000000

0x021C8110: /dev/mem opened.
Memory mapped at address 0xb6fb0000.
Read at address 0x021C8110 (0xb6fb0110): 0x00000000
0x021C8114: /dev/mem opened.

0x021C8120: /dev/mem opened.
Memory mapped at address 0xb6f4b000.
Read at address 0x021C8120 (0xb6f4b120): 0x00000000

0x021C8130: /dev/mem opened.
Memory mapped at address 0xb6f2f000.
Read at address 0x021C8130 (0xb6f2f130): 0x00000000

0x021C8140: /dev/mem opened.
Memory mapped at address 0xb6fe8000.
Read at address 0x021C8140 (0xb6fe8140): 0x00000000

0x021C8150: /dev/mem opened.
Memory mapped at address 0xb6f3d000.
Read at address 0x021C8150 (0xb6f3d150): 0x00000000

0x021C8160: /dev/mem opened.
Memory mapped at address 0xb6fa0000.
Read at address 0x021C8160 (0xb6fa0160): 0x00800010

0x021C8170: /dev/mem opened.
Memory mapped at address 0xb6f0d000.
Read at address 0x021C8170 (0xb6f0d170): 0x00FF00FF

0x021C8180: /dev/mem opened.
Memory mapped at address 0xb6f9c000.
Read at address 0x021C8180 (0xb6f9c180): 0xE7F21030

0x021C8190: /dev/mem opened.
Memory mapped at address 0xb6fab000.
Read at address 0x021C8190 (0xb6fab190): 0x00000000

0x021C81A0: /dev/mem opened.
Memory mapped at address 0xb6f5c000.
Read at address 0x021C81A0 (0xb6f5c1a0): 0x00000000

0x021C81B0: /dev/mem opened.
Memory mapped at address 0xb6f15000.
Read at address 0x021C81B0 (0xb6f151b0): 0x8D0000F8

0x021C81C0: /dev/mem opened.
Memory mapped at address 0xb6f17000.
Read at address 0x021C81C0 (0xb6f171c0): 0x04000000

0x021C81D0: /dev/mem opened.
Memory mapped at address 0xb6fd8000.
Read at address 0x021C81D0 (0xb6fd81d0): 0x0E00000F

0x021C81E0: /dev/mem opened.
Memory mapped at address 0xb6f59000.
Read at address 0x021C81E0 (0xb6f591e0): 0x012001E0

0x021C81F0: /dev/mem opened.
Memory mapped at address 0xb6fda000.
Read at address 0x021C81F0 (0xb6fda1f0): 0x00000780

0x021C8200: /dev/mem opened.
Memory mapped at address 0xb6fdc000.
Read at address 0x021C8200 (0xb6fdc200): 0x0100000F

0x021C8210: /dev/mem opened.
Memory mapped at address 0xb6f2d000.
Read at address 0x021C8210 (0xb6f2d210): 0x00000000

0x021C8220: /dev/mem opened.
Memory mapped at address 0xb6f58000.
Read at address 0x021C8220 (0xb6f58220): 0x00000000

0x021C8230: /dev/mem opened.
Memory mapped at address 0xb6fbc000.
Read at address 0x021C8230 (0xb6fbc230): 0x00000000

0x021C8240: /dev/mem opened.
Memory mapped at address 0xb6f0f000.
Read at address 0x021C8240 (0xb6f0f240): 0x00FFFFFF

0x021C8250: /dev/mem opened.
Memory mapped at address 0xb6fc5000.
Read at address 0x021C8250 (0xb6fc5250): 0x00000000

Re: imx6ul LCDif controller stop working after reboot

mhe — Wed, 06 Aug 2025 02:08:41 GMT

the display timing is

clock-frequency = <37000000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <154>;
hback-porch = <120>;
hsync-len = <100>;
vfront-porch = <20>;
vback-porch = <15>;
vsync-len = <10>;
de-active = <1>;
pixelclk-active = <1>;
vsync-active = <0>;
hsync-active = <0>;

Re: imx6ul LCDif controller stop working after reboot

mhe — Wed, 06 Aug 2025 09:04:12 GMT

I found only 37MHZ could cause the problem, frequency higher 37.5M 60M or lower 36.5 would not cause the problem. Anyone could help find the root cause?

When it fails, softreset by writing LCD_CTRL register and enable by fbset would not help.

topic Re: imx6ul LCDif controller stop working after reboot in i.MX Processors

imx6ul LCDif controller stop working after reboot

Re: imx6ul LCDif controller stop working after reboot

Re: imx6ul LCDif controller stop working after reboot