topic Re: SPI Chip Select Toggling Problem on imx8mplus in i.MX Processors

SPI Chip Select Toggling Problem on imx8mplus

Baha_Yenioglu — Mon, 04 Aug 2025 14:29:14 GMT

Greetings,
I’m currently trying to communicate between the i.MX 8M Plus and some module via SPI. However, I’m seeing that the chip-select line toggles on each byte transfer, when it should stay low for the entire transaction for the command and its arguments. Is this the default behavior? If so, how can I keep CS asserted throughout the whole communication? Also, what's the default SPI_MODE in terms of phase and polarity of the clock ?

Re: SPI Chip Select Toggling Problem on imx8mplus

Chavira — Mon, 04 Aug 2025 17:00:04 GMT

Hi @Baha_Yenioglu!

Thank you for reaching out to NXP Support!

Could you please share your device tree configuration?
I've encountered similar behavior before when the configuration doesn't follow the structure shown in the example below:

&ecspi2 { #address-cells = <1>; #size-cells = <0>; fsl,spi-num-chipselects = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; status = "okay"; spidev1: spi@0 { reg = <0>; compatible = "rohm,dh2228fv"; spi-max-frequency = <500000>; }; }; ... pinctrl_ecspi2: ecspi2grp { fsl,pins = < MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 >; }; pinctrl_ecspi2_cs: ecspi2cs { fsl,pins_SS0__GPIO5_IO13 0x40000 >; };

Let me know if your configuration differs or if you need help adapting it.

Best regards,
Chavira

Re: SPI Chip Select Toggling Problem on imx8mplus

Baha_Yenioglu — Tue, 05 Aug 2025 06:05:05 GMT

After I applied this structure to my dts, CS stayed stay low for the entire transaction.
Thanks..