topic Re: ECSPI_SCLK signal integrity in i.MX Processors

ECSPI_SCLK signal integrity

_eg — Tue, 29 Jul 2025 04:02:28 GMT

Hi,

I'm using the i.MX8M mini.

I measured the waveform of SCLK and MISO at the i.MX end.
The SCLK is output by i.MX as the master, but there are distortions such as glitches on the rising edge.

When capturing data form MISO, does the i.MX8 use this SCLK waveform?
Is my unerstanding correct that the internal circuit driving the data acquisition uses a clean singal that is isolated by buffers, and is not affected by external reflections?

CH1 (Yellow) : SCLK
CH2 (Blue): MISO

_eg_0-1753761114517.png

Thanks,

Re: ECSPI_SCLK signal integrity

joanxie — Wed, 30 Jul 2025 02:54:39 GMT

1)When capturing data form MISO, does the i.MX8 use this SCLK waveform?

>yes, refer to the reference manual, The ECSPI master uses the Chip Select (SS) signal to enable an external SPI device, and uses the SCLK signal to transfer data in and out of the Shift register.
2)Is my unerstanding correct that the internal circuit driving the data acquisition uses a clean singal that is isolated by buffers, and is not affected by external reflections?

> the signal integrity issues present at the pin would be affected by external, so you need to double check your HW design

Re: ECSPI_SCLK signal integrity

_eg — Wed, 30 Jul 2025 04:15:32 GMT

Dear janxie,

Thank you for your reply.
I understand that ECSPI uses SCLK signal for Shift register.
And SCLK wavefore is important for Slave device.

I'd like to know the i.MX inside diagram.
Figure 1. is my understanding.
Do you mean that Figure 2 is correct?

_eg_2-1753848826403.png

_eg_3-1753848838651.png

Thanks,

Re: ECSPI_SCLK signal integrity

joanxie — Sat, 02 Aug 2025 01:49:00 GMT

refer to the RM, I only find this diagram, though I don't have internal design diagram, but the ecspi design can provide the clean signal to the SCLK, if all of your boards get the jitter, should check the HW design or measurement tools, if only one or two boards have this issue, maybe you can do the AB test to confirm if this issue is related to the chip

joanxie_0-1754032967239.png

Re: ECSPI_SCLK signal integrity

_eg — Wed, 06 Aug 2025 12:11:24 GMT

Dear janxie,

Thank you for your reply.
I understand that we currently don't have the internal design diagram, so we cannot resolve my question at this time.

Best Regards,