topic OPERATION_MODE of DDRC_STAT remains at Init and does not become Normal on i.MX7D in i.MX Processors

OPERATION_MODE of DDRC_STAT remains at Init and does not become Normal on i.MX7D

tamotsu — Fri, 01 Aug 2025 05:47:14 GMT

Hi.

It uses DDR3L.

I used the configuration file "MX7D_DDR3_register_programming_aid_v1_2.xlsx" and "/mx7dsabresd/imximage.cfg" in u-boot as references.

At the end of the setup, I read DDRC_STAT, but OPERATING_MODE remains Init.

How do I get to Normal mode?

I think this mode probably doesn't become Normal, so reading 0x80000000 causes the computer to freeze.

Best regards.

Re: OPERATION_MODE of DDRC_STAT remains at Init and does not become Normal on i.MX7D

pengyong_zhang — Fri, 01 Aug 2025 08:18:53 GMT

Hi @tamotsu

What changes did you make to the code?and How do you read the register value?

B.R

Re: OPERATION_MODE of DDRC_STAT remains at Init and does not become Normal on i.MX7D

patterson123 — Fri, 01 Aug 2025 10:14:15 GMT

The user wants a short paragraph summarizing the detailed response about their DDR initialization issue.

I need to extract the key points from the previous response:
* **The Problem:** The DDR controller's `OPERATING_MODE` is stuck in `Init` mode, meaning memory initialization failed.
* **The Cause:** This usually happens due to an incomplete initialization sequence or incorrect register values.
* **The Solution:** The user must ensure their code correctly initiates the training sequence by setting the `DDRC_MSTR` register. They should then poll the `DDRC_STAT` register, waiting for the `OPERATING_MODE` to transition to `Normal`. Double-checking the register values from the programming aid is also a critical step.

I'll combine these points into a single, concise paragraph.
Your DDR controller's `OPERATING_MODE` is stuck in `Init` because the memory initialization sequence has failed to complete. This is most often caused by an incomplete code sequence or incorrect register values. To fix it, ensure your code correctly initiates the memory training by writing the appropriate value to the `DDRC_MSTR` register. You must then poll the `DDRC_STAT` register, waiting for the `OPERATING_MODE` to transition to `Normal`, which signals a successful initialization. Double-checking your timing and calibration register values against the provided programming aid is also a critical step.

Re: OPERATION_MODE of DDRC_STAT remains at Init and does not become Normal on i.MX7D

tamotsu — Mon, 04 Aug 2025 00:20:43 GMT

Hi patterson123.

I appreciate the specific advice.

I'll try again following your advice and will get back to you with the results.

Best regards.

Re: OPERATION_MODE of DDRC_STAT remains at Init and does not become Normal on i.MX7D

tamotsu — Mon, 04 Aug 2025 01:35:35 GMT

Hi Pengyong_zhang.

Thanks.

First, since I was using the same Micron DDR3, I wrote the code according to the "i.MX7D DDR Controller Configuration Spreadsheet."

However, I was unable to access the DDR. At the time, I was unaware that initialization had not yet finished.

Next, I found the SABRE board settings in u-boot, changed it to this code and tried it.

However, this was also not accessible. I confirmed that initialization had not yet finished.

Below is the write code.

DDRC_MSTR : 0x01040001

DDRC_DFIUUPD0: 0x80400003

DDRC_DFIUUPD1: 0x00100020

DDRC_DFIUUPD2: 0x80400004

DDRC_RFSHTMG: 0x00400046

DDRC_MP_PCTRL_0: 0x00000001

DDRC_INIT0: 0x00020083

DDRC_INIT1: 0x00690000

DDRC_INIT3: 0x09300004

DDRC_INIT2: 0x00000000

DDRC_INIT4: 0x04080000

DDRC_INIT5: 0x00200004

DDRC_RANKCTL: 0x0000033F

DDRC_DRAMTMG0: 0x09081109

DDRC_DRAMTMG1: 0x0007020D

DDRC_DRAMTMG2: 0x03040407

DDRC_DRAMTMG3: 0x00002006

DDRC_DRAMTMG4: 0x04020205

DDRC_DRAMTMG5: 0x03030202

DDRC_DRAMTMG8: 0x00000803

DDRC_ZQCTL0: 0x00800020

DDRC_ZQCTL1: 0x02000100

DDRC_DFITMG0: 0x02098204

DDRC_DFITMG1: 0x00030303

DDRC_ADDRMAP0: 0x0000001F

DDRC_ADDRMAP1: 0x00080808

DDRC_ADDRMAP5: 0x04040404

DDRC_ADDRMAP6: 0x0F040404

DDRC_ODTCFG: 0x06000604

DDRC_ODTMAP: 0x00000001

SRC_DDRC_RCR: 0x00000000

I read DDRC_STAT here, but it was not set to Normal.

Best regards.