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    <title>topic Re: Pinout Differences Between MIMX8ML8DVNLZAB and 8MPLUSLPD4-CPU Eval Board in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Pinout-Differences-Between-MIMX8ML8DVNLZAB-and-8MPLUSLPD4-CPU/m-p/2143892#M239707</link>
    <description>&lt;P&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;Here I think there is a little confusion on your side, please note that all 35 VDD_SOC pads are tied together on the EVK, so in your design it should be the same, no matter the pad number on the schematic since all are VDD_SOC.&lt;BR /&gt;&lt;BR /&gt;Best regards/Saludos,&lt;BR /&gt;Aldo.&lt;/P&gt;</description>
    <pubDate>Wed, 30 Jul 2025 21:05:36 GMT</pubDate>
    <dc:creator>AldoG</dc:creator>
    <dc:date>2025-07-30T21:05:36Z</dc:date>
    <item>
      <title>Pinout Differences Between MIMX8ML8DVNLZAB and 8MPLUSLPD4-CPU Eval Board</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Pinout-Differences-Between-MIMX8ML8DVNLZAB-and-8MPLUSLPD4-CPU/m-p/2142894#M239677</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I’ve noticed some discrepancies between the pin naming/assignment in the datasheet for the &lt;STRONG&gt;MIMX8ML8DVNLZAB&lt;/STRONG&gt; processor and the schematic of the &lt;STRONG&gt;8MPLUSLPD4-CPU&lt;/STRONG&gt; evaluation board. Specifically, certain power pins (like &lt;STRONG&gt;VDD_SOC_17&lt;/STRONG&gt;) are assigned to different locations.&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;The pinout in the&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;datasheet&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;matches exactly with my own PCB design.&lt;/LI&gt;&lt;LI&gt;However, in the&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;8MPLUSLPD4-CPU&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;eval board schematic, some power pins (e.g., VDD_SOC_17) seem to be assigned to different pins compared to the datasheet.&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;What could be the reason for this difference?&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;Is it due to a different package type being used?&lt;/LI&gt;&lt;LI&gt;Is there a special revision or variant of the processor for the eval board?&lt;/LI&gt;&lt;LI&gt;Or is this a documentation error?&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;If anyone has experienced this or can provide clarification, I’d appreciate your help.&lt;/P&gt;&lt;P&gt;Thank you!&lt;BR /&gt;&lt;BR /&gt;eva board compute module&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="electronx_0-1753813022217.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/350060i89C1B8A5C8E06AFD/image-size/medium?v=v2&amp;amp;px=400" role="button" title="electronx_0-1753813022217.png" alt="electronx_0-1753813022217.png" /&gt;&lt;/span&gt;&lt;BR /&gt;&lt;BR /&gt;Datasheet&amp;nbsp;MIMX8ML8DVNLZAB&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="electronx_1-1753813049759.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/350061i99E05EEEB16D27DE/image-size/medium?v=v2&amp;amp;px=400" role="button" title="electronx_1-1753813049759.png" alt="electronx_1-1753813049759.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 29 Jul 2025 18:19:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Pinout-Differences-Between-MIMX8ML8DVNLZAB-and-8MPLUSLPD4-CPU/m-p/2142894#M239677</guid>
      <dc:creator>electronx</dc:creator>
      <dc:date>2025-07-29T18:19:25Z</dc:date>
    </item>
    <item>
      <title>Re: Pinout Differences Between MIMX8ML8DVNLZAB and 8MPLUSLPD4-CPU Eval Board</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Pinout-Differences-Between-MIMX8ML8DVNLZAB-and-8MPLUSLPD4-CPU/m-p/2143892#M239707</link>
      <description>&lt;P&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;Here I think there is a little confusion on your side, please note that all 35 VDD_SOC pads are tied together on the EVK, so in your design it should be the same, no matter the pad number on the schematic since all are VDD_SOC.&lt;BR /&gt;&lt;BR /&gt;Best regards/Saludos,&lt;BR /&gt;Aldo.&lt;/P&gt;</description>
      <pubDate>Wed, 30 Jul 2025 21:05:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Pinout-Differences-Between-MIMX8ML8DVNLZAB-and-8MPLUSLPD4-CPU/m-p/2143892#M239707</guid>
      <dc:creator>AldoG</dc:creator>
      <dc:date>2025-07-30T21:05:36Z</dc:date>
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