topic Re: TP_RESET Pin LOW during Suspend to RAM in i.MX Processors

TP_RESET Pin LOW during Suspend to RAM

Ram2 — Mon, 28 Jul 2025 09:57:48 GMT

Hi Team

One question about the TP_RESET pin is low when your system enters Sleep to Mem

But we didn't put it into low level when entering suspend mode.

Could you clarify to me who makes TP_RESET pin to low when your system enters Sleep to Mem from Soc side?

How to retain the GPIO states during suspend to RAM and how to reinitialise the GPIOs states after waking from the suspend to ram.

&lsio_gpio5 9 0x0000>;

TP_RESET line (GPIO5_IO09) is unexpectedly going low during Suspend-to-RAM (S2R)

Re: TP_RESET Pin LOW during Suspend to RAM

JorgeCas — Mon, 28 Jul 2025 18:29:00 GMT

Hello,

Could you please share which processor are you using?

Best regards.

Re: TP_RESET Pin LOW during Suspend to RAM

Ram2 — Tue, 29 Jul 2025 06:38:25 GMT

Hi @JorgeCas

We are currently working on iMX8qxpC0mek

Re: TP_RESET Pin LOW during Suspend to RAM

JorgeCas — Tue, 29 Jul 2025 17:13:44 GMT

Hello,

This behavior is handled by SCFW, specifically sc_pad_iso_t iso.

This defines how the pad behaves in low-power modes (like suspend or sleep). The available options are:

ISO_OFF - SC_PAD_ISO_OFF
ISO_EARLY - SC_PAD_ISO_EARLY
ISO_LATE - SC_PAD_ISO_LATE
ISO_ON - SC_PAD_ISO_ON

This isolation setting helps to manage power leakage when the system enters into low-power states and ensures that pads do not consume unnecessary power when are not in use.

Please take a look in the next post:

System Controller Firmware 101 - Pad configuration service - NXP Community

Best regards.