<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic NXP IMX DDR Tool MX8ULP issues in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/NXP-IMX-DDR-Tool-MX8ULP-issues/m-p/2142836#M239671</link>
    <description>&lt;P&gt;I am working with the i.MX8ULP processor (MIMX8UD3CVP08SC, revision A2) on my custom PCB. I am working with (effectively) the same DDR as the EVK (MT53E512M32D1ZW-046AUT:B), however I am using the LPDDR4x mode.&lt;BR /&gt;&lt;BR /&gt;I am having trouble with running the NXP IMX DDR Tool, receiving chopped off debug, and hanging at the log pasted below.&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;LI-CODE lang="markup"&gt;[RESULT] Download is complete
Waiting for the target board boot...

===================hardware_init=====================

OCK Set BUCK3 to 0.9v
hardware_init exit

*************************************************************************

*************************************************************************

*************************************************************************
       NXP DDR Tool V1.00
       Built on Apr 28 2023 11:20:51
*************************************************************************

Waiting for board configuration from PC-end...&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The NXP IMX DDR Tool only accommodates for revisions A0 and A1. Is there an updated IMX DDR Tool for the A2 revision?&lt;BR /&gt;&lt;BR /&gt;I have successfully set up my COM communication for the A-Core LPUART7. Does this look right?&lt;/P&gt;&lt;LI-CODE lang="markup"&gt;memory set	0x298c00bc	32	0x00000443	#PTE15__LPUART7_RX       					
memory set	0x298c09dc	32	0x00000003	#PTE15__LPUART7_RX       					
memory set	0x298c00b8	32	0x00000443	#PTE14__LPUART7_TX       					
memory set	0x298c09e0	32	0x00000003	#PTE14__LPUART7_TX       		
sysparam set	debug_uart	6		#LPUART7 : index from 0 ('0' = UART1, '1' = UART2 and so on)	&lt;/LI-CODE&gt;</description>
    <pubDate>Tue, 29 Jul 2025 15:37:45 GMT</pubDate>
    <dc:creator>ksingh</dc:creator>
    <dc:date>2025-07-29T15:37:45Z</dc:date>
    <item>
      <title>NXP IMX DDR Tool MX8ULP issues</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/NXP-IMX-DDR-Tool-MX8ULP-issues/m-p/2142836#M239671</link>
      <description>&lt;P&gt;I am working with the i.MX8ULP processor (MIMX8UD3CVP08SC, revision A2) on my custom PCB. I am working with (effectively) the same DDR as the EVK (MT53E512M32D1ZW-046AUT:B), however I am using the LPDDR4x mode.&lt;BR /&gt;&lt;BR /&gt;I am having trouble with running the NXP IMX DDR Tool, receiving chopped off debug, and hanging at the log pasted below.&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;LI-CODE lang="markup"&gt;[RESULT] Download is complete
Waiting for the target board boot...

===================hardware_init=====================

OCK Set BUCK3 to 0.9v
hardware_init exit

*************************************************************************

*************************************************************************

*************************************************************************
       NXP DDR Tool V1.00
       Built on Apr 28 2023 11:20:51
*************************************************************************

Waiting for board configuration from PC-end...&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The NXP IMX DDR Tool only accommodates for revisions A0 and A1. Is there an updated IMX DDR Tool for the A2 revision?&lt;BR /&gt;&lt;BR /&gt;I have successfully set up my COM communication for the A-Core LPUART7. Does this look right?&lt;/P&gt;&lt;LI-CODE lang="markup"&gt;memory set	0x298c00bc	32	0x00000443	#PTE15__LPUART7_RX       					
memory set	0x298c09dc	32	0x00000003	#PTE15__LPUART7_RX       					
memory set	0x298c00b8	32	0x00000443	#PTE14__LPUART7_TX       					
memory set	0x298c09e0	32	0x00000003	#PTE14__LPUART7_TX       		
sysparam set	debug_uart	6		#LPUART7 : index from 0 ('0' = UART1, '1' = UART2 and so on)	&lt;/LI-CODE&gt;</description>
      <pubDate>Tue, 29 Jul 2025 15:37:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/NXP-IMX-DDR-Tool-MX8ULP-issues/m-p/2142836#M239671</guid>
      <dc:creator>ksingh</dc:creator>
      <dc:date>2025-07-29T15:37:45Z</dc:date>
    </item>
    <item>
      <title>Re: NXP IMX DDR Tool MX8ULP issues</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/NXP-IMX-DDR-Tool-MX8ULP-issues/m-p/2142949#M239678</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;There is not an updated DDR Tool version for i.MX8ULP and you customization to use LPUART 7 is correct.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I suggest you check the connection between your board and the PC (data and debug cables).&lt;/P&gt;
&lt;P&gt;Best regards.&lt;/P&gt;</description>
      <pubDate>Tue, 29 Jul 2025 20:33:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/NXP-IMX-DDR-Tool-MX8ULP-issues/m-p/2142949#M239678</guid>
      <dc:creator>JorgeCas</dc:creator>
      <dc:date>2025-07-29T20:33:53Z</dc:date>
    </item>
  </channel>
</rss>

