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    <title>i.MX Processors中的主题 Re: iMX93 LPDDR4x config</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX93-LPDDR4x-config/m-p/2137565#M239428</link>
    <description>&lt;P&gt;I now have half the memory working (1GB) by reducing the DDR speed to 3200. If I set the number of ranks to 1 and the memory size the 8Gb then the DDR config tests all pass. If I set the ranks to 2 then the tests start failing.&lt;/P&gt;</description>
    <pubDate>Mon, 21 Jul 2025 16:12:24 GMT</pubDate>
    <dc:creator>andyclayton</dc:creator>
    <dc:date>2025-07-21T16:12:24Z</dc:date>
    <item>
      <title>iMX93 LPDDR4x config</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX93-LPDDR4x-config/m-p/2134932#M239320</link>
      <description>&lt;P&gt;I have a custom iMx93 board with 16Gb LPDDR4x fitted (single rank) which works fine, however when I try to use a dual rank LPDDR4x device on the same board the DDR config tool fails the firmware init tests, just hanging on the following command (mw 204B2BB8,1). The board is routed for 2 CS signals and 2 CKE signals for the two ranks. The LPDDR4X part I am having problems with is JSC&amp;nbsp;JSL4BAG167ZAMF-05A, the Micron alternative (MT53E1G16D1FW-046 AIT:A) works fine so I know the layout is good.&lt;/P&gt;</description>
      <pubDate>Wed, 16 Jul 2025 10:38:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX93-LPDDR4x-config/m-p/2134932#M239320</guid>
      <dc:creator>andyclayton</dc:creator>
      <dc:date>2025-07-16T10:38:05Z</dc:date>
    </item>
    <item>
      <title>Re: iMX93 LPDDR4x config</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX93-LPDDR4x-config/m-p/2134952#M239321</link>
      <description>&lt;P&gt;Here's the debug output from the config tool :-&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;P&gt;#################### Result for: phy_init ###### Run 1 #############################################Microsoft Windows [Version 10.0.26100.4652]&lt;/P&gt;&lt;P&gt;(c) Microsoft Corporation. All rights reserved.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;C:\nxp\i.MX_CFG_25.03\bin&amp;gt;prompt test-prefix :&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;test-prefix : "C:/nxp/i.MX_CFG_25.03/bin/python3/python" "C:/nxp/i.MX_CFG_25.03/bin/python3/memtool/memtool_entry.py" -t "runtest" -d "C:/ProgramData/NXP/mcu_data_25.03/processors/MIMX9332xxxxM/ksdk2_0/mem_validation/ddrc" -p "C:/Users/andyc/AppData/Local/Temp/mem_validation/phy_training_phy_test_0_0_.log" -l DEBUG "C:/Users/andyc/AppData/Local/Temp/mem_validation/connect.json" "C:/Users/andyc/AppData/Local/Temp/mem_validation/test.json" "C:/Users/andyc/AppData/Local/Temp/mem_validation/phy.json" "C:/Users/andyc/AppData/Local/Temp/mem_validation/ddrc_registers.json" "C:/Users/andyc/AppData/Local/Temp/mem_validation/ddrc_config.json" "C:/Users/andyc/AppData/Local/Temp/mem_validation/ddrc_config_in.json"&lt;/P&gt;&lt;P&gt;INFO memtool.utils.helper *****C:/Users/andyc/AppData/Local/Temp/mem_validation/connect.json&lt;/P&gt;&lt;P&gt;INFO memtool.utils.helper *****C:/Users/andyc/AppData/Local/Temp/mem_validation/test.json&lt;/P&gt;&lt;P&gt;INFO memtool.utils.helper *****C:/Users/andyc/AppData/Local/Temp/mem_validation/phy.json&lt;/P&gt;&lt;P&gt;INFO memtool.utils.helper *****C:/Users/andyc/AppData/Local/Temp/mem_validation/ddrc_registers.json&lt;/P&gt;&lt;P&gt;INFO memtool.utils.helper *****C:/Users/andyc/AppData/Local/Temp/mem_validation/ddrc_config.json&lt;/P&gt;&lt;P&gt;INFO memtool.utils.helper *****C:/Users/andyc/AppData/Local/Temp/mem_validation/ddrc_config_in.json&lt;/P&gt;&lt;P&gt;DEBUG memtool.common.factories new instance -&amp;gt; {inst}&lt;/P&gt;&lt;P&gt;INFO memtool.processor.imx9.imx9_processor Xls mapping load time 0.010644&lt;/P&gt;&lt;P&gt;DEBUG memtool.rpa.xls_engine_mx9 Set Register Configuration!E8 to Disable&lt;/P&gt;&lt;P&gt;INFO memtool.processor.imx9.imx9_processor Config time 0.000295&lt;/P&gt;&lt;P&gt;INFO memtool.processor.imx9.imx9_processor DS file time 0.215430&lt;/P&gt;&lt;P&gt;DEBUG memtool.processor.imx9.imx9_processor freq_0 set to 3200&lt;/P&gt;&lt;P&gt;INFO memtool.phyinit.phy_init Run phyinit for 2022.01\lpddr4x&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.phy_init Shared library C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX9332xxxxM\ksdk2_0\mem_validation\ddrc\phyinit\sharedlib\phyinit_2022.01_lpddr4x.dll&lt;/P&gt;&lt;P&gt;DEBUG memtool.common.factories new instance -&amp;gt; {inst}&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.phy_init PHY config file C:\Users\andyc\AppData\Local\Temp\mem_validation\phy_config_final.json&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.phy_init Phyinit output file C:\Users\andyc\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txt&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.phy_init Retention output file C:\Users\andyc\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txt&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Parse phyinit output file C:\Users\andyc\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txt&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Parse retention output file C:\Users\andyc\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txt&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Parse state A_BRING_UP_POWER&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Parse state C_PHY_INIT_CONFIG(307)&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x20fc to file C:\Users\andyc\AppData\Local\Temp\mem_validation\phy_init.c&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0xda5 to file C:\Users\andyc\AppData\Local\Temp\mem_validation\phy_init.json&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Parse state LOAD_IMEM_1(468)&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Parse state D_LOAD_IMEM_1D(488)&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Write IMEM 1D as bin size 0x8000 to file C:\Users\andyc\AppData\Local\Temp\mem_validation\imem_1d.bin&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Write IMEM 1D as txt size 0x6eb52 to file C:\Users\andyc\AppData\Local\Temp\mem_validation\imem_1d.txt&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Parse state PHASE.E_SET_DFI_CLOCK(16873)&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1(16892)&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1D(16908)&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Write DMEM 1D as bin size 0x67c to file C:\Users\andyc\AppData\Local\Temp\mem_validation\dmem_1d.bin&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Write DMEM 1D as txt size 0x5394 to file C:\Users\andyc\AppData\Local\Temp\mem_validation\dmem_1d.txt&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Parse state PHASE.G_EXEC_FW(17739)&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Parse state PHASE.E_SET_DFI_CLOCK(17815)&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Parse state PHASE.D_LOAD_IMEM_2(17819)&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Parse state PHASE.D_LOAD_IMEM_2D(17837)&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Write IMEM 2D as txt size 0x6c68b to file C:\Users\andyc\AppData\Local\Temp\mem_validation\imem_2d.txt&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Write IMEM 2D as bin size 0x8000 to file C:\Users\andyc\AppData\Local\Temp\mem_validation\imem_2d.bin&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Parse state PHASE.PHASE.F_LOAD_DMEM_2(34222)&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Parse state PHASE.D_LOAD_DMEM_2D(34243)&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Write DMEM 2D as bin size 0x580 to file C:\Users\andyc\AppData\Local\Temp\mem_validation\dmem_2d.bin&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Write DMEM 2D as txt size 0x460a to file C:\Users\andyc\AppData\Local\Temp\mem_validation\dmem_2d.txt&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Parse state PHASE.PHASE.G_EXEC_FW(34948)&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Parse state PHASE.PHASE.I_LOAD_PIE(35014)&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Write PIE as txt size 0x42c3 to file C:\Users\andyc\AppData\Local\Temp\mem_validation\pie.txt&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Write PIE as txt size 0x8d02 to file C:\Users\andyc\AppData\Local\Temp\mem_validation\pie.json&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Parse state PHASE.H_READ_MSG_BLOCK(35597)&lt;/P&gt;&lt;P&gt;DEBUG memtool.phyinit.out_parser Parse retention register list&lt;/P&gt;&lt;P&gt;INFO memtool.comm.serial_channel Using serial: COM9&lt;/P&gt;&lt;P&gt;DEBUG memtool.common.factories new instance -&amp;gt; {inst}&lt;/P&gt;&lt;P&gt;DEBUG memtool.common.factories new instance -&amp;gt; {inst}&lt;/P&gt;&lt;P&gt;DEBUG memtool.common.factories new instance -&amp;gt; {inst}&lt;/P&gt;&lt;P&gt;DEBUG memtool.comm.serial_channel Channel is not alive&lt;/P&gt;&lt;P&gt;DEBUG spsdk.utils.interfaces.device.usb_device Closing the Interface: OO Blank 93 (0x1FC9, 0x014E)path=b'\\\\?\\hid#vid_1fc9&amp;amp;pid_014e#6&amp;amp;13db141b&amp;amp;0&amp;amp;0000#{4d1e55b2-f16f-11cf-88cb-001111000030}' sn=''&lt;/P&gt;&lt;P&gt;DEBUG memtool.comm.serial_channel ==================hardware_init=======================&lt;/P&gt;&lt;P&gt;DEBUG memtool.comm.serial_channel&lt;/P&gt;&lt;P&gt;DEBUG memtool.comm.serial_channel Power up ddr...&lt;/P&gt;&lt;P&gt;DEBUG memtool.comm.serial_channel&lt;/P&gt;&lt;P&gt;DEBUG memtool.comm.serial_channel DDRMIX power on done...&lt;/P&gt;&lt;P&gt;DEBUG memtool.comm.serial_channel&lt;/P&gt;&lt;P&gt;DEBUG memtool.comm.serial_channel DDRPHY coldreset...&lt;/P&gt;&lt;P&gt;DEBUG memtool.comm.serial_channel&lt;/P&gt;&lt;P&gt;DEBUG memtool.comm.serial_channel Reset and configure LPI2C...&lt;/P&gt;&lt;P&gt;DEBUG memtool.comm.serial_channel&lt;/P&gt;&lt;P&gt;DEBUG memtool.comm.serial_channel&lt;/P&gt;&lt;P&gt;DEBUG memtool.comm.serial_channel&lt;/P&gt;&lt;P&gt;DEBUG memtool.comm.serial_channel ********Found PMIC PCA945X**********&lt;/P&gt;&lt;P&gt;DEBUG memtool.comm.serial_channel&lt;/P&gt;&lt;P&gt;DEBUG memtool.comm.serial_channel Set VDDQ to 0.6V for LPDDR4X&lt;/P&gt;&lt;P&gt;DEBUG memtool.comm.serial_channel&lt;/P&gt;&lt;P&gt;DEBUG memtool.comm.serial_channel ==================hardware_init exit==================&lt;/P&gt;&lt;P&gt;DEBUG memtool.comm.serial_channel&lt;/P&gt;&lt;P&gt;DEBUG memtool.comm.serial_channel&lt;/P&gt;&lt;P&gt;DEBUG memtool.comm.serial_channel&lt;/P&gt;&lt;P&gt;DEBUG memtool.comm.serial_channel&lt;/P&gt;&lt;P&gt;DEBUG memtool.comm.serial_channel Channel is alive&lt;/P&gt;&lt;P&gt;DEBUG memtool.comm.serial_channel Executing: mw204B2BB8,1&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Wed, 16 Jul 2025 11:02:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX93-LPDDR4x-config/m-p/2134952#M239321</guid>
      <dc:creator>andyclayton</dc:creator>
      <dc:date>2025-07-16T11:02:54Z</dc:date>
    </item>
    <item>
      <title>Re: iMX93 LPDDR4x config</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX93-LPDDR4x-config/m-p/2137198#M239415</link>
      <description>&lt;P&gt;Dual rank single channel devices are supported therefore, 16Gb/2GB density can be also achieved by using a dual rank single channel device with 16-row addresses (R0 - R15).&lt;/P&gt;
&lt;P&gt;Have you configurate the LPRRD4X proper, you can share your configuration to us first.&lt;/P&gt;</description>
      <pubDate>Mon, 21 Jul 2025 08:28:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX93-LPDDR4x-config/m-p/2137198#M239415</guid>
      <dc:creator>Rita_Wang</dc:creator>
      <dc:date>2025-07-21T08:28:58Z</dc:date>
    </item>
    <item>
      <title>Re: iMX93 LPDDR4x config</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX93-LPDDR4x-config/m-p/2137227#M239418</link>
      <description>&lt;P&gt;Configuration attached. I've also tried single rank 8Gb/1GB settings as well.&lt;/P&gt;</description>
      <pubDate>Mon, 21 Jul 2025 08:50:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX93-LPDDR4x-config/m-p/2137227#M239418</guid>
      <dc:creator>andyclayton</dc:creator>
      <dc:date>2025-07-21T08:50:54Z</dc:date>
    </item>
    <item>
      <title>Re: iMX93 LPDDR4x config</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX93-LPDDR4x-config/m-p/2137474#M239425</link>
      <description>&lt;P&gt;Found the problem, the serial port was dying during the test.&lt;/P&gt;</description>
      <pubDate>Mon, 21 Jul 2025 13:14:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX93-LPDDR4x-config/m-p/2137474#M239425</guid>
      <dc:creator>andyclayton</dc:creator>
      <dc:date>2025-07-21T13:14:24Z</dc:date>
    </item>
    <item>
      <title>Re: iMX93 LPDDR4x config</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX93-LPDDR4x-config/m-p/2137565#M239428</link>
      <description>&lt;P&gt;I now have half the memory working (1GB) by reducing the DDR speed to 3200. If I set the number of ranks to 1 and the memory size the 8Gb then the DDR config tests all pass. If I set the ranks to 2 then the tests start failing.&lt;/P&gt;</description>
      <pubDate>Mon, 21 Jul 2025 16:12:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX93-LPDDR4x-config/m-p/2137565#M239428</guid>
      <dc:creator>andyclayton</dc:creator>
      <dc:date>2025-07-21T16:12:24Z</dc:date>
    </item>
    <item>
      <title>Re: iMX93 LPDDR4x config</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX93-LPDDR4x-config/m-p/2138837#M239484</link>
      <description>&lt;P&gt;Good new and good job!&lt;/P&gt;</description>
      <pubDate>Wed, 23 Jul 2025 02:25:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX93-LPDDR4x-config/m-p/2138837#M239484</guid>
      <dc:creator>Rita_Wang</dc:creator>
      <dc:date>2025-07-23T02:25:55Z</dc:date>
    </item>
    <item>
      <title>回复： iMX93 LPDDR4x config</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX93-LPDDR4x-config/m-p/2249312#M242435</link>
      <description>&lt;P&gt;HI&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/57446"&gt;@andyclayton&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;1.&lt;SPAN&gt;May I ask if you successfully transplanted JSL4BAG167ZAMF, and if you could share your experience?&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 26 Nov 2025 11:01:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX93-LPDDR4x-config/m-p/2249312#M242435</guid>
      <dc:creator>yrj</dc:creator>
      <dc:date>2025-11-26T11:01:22Z</dc:date>
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