https://community.nxp.com/t5/i-MX-Processors/iMX95-CA-bit-swapping/m-p/2133809#M239279 <P>Hi NXP,</P><P>Is bit swapping of the CA[6:0] pins allowed for the LPDDR5?</P><P>Apart from the mapping of the EVK, are there any successful bit mappings that can work for the iMX95?</P><P>Thanks,</P><P>Simon</P> Tue, 15 Jul 2025 06:38:59 GMT simonng 2025-07-15T06:38:59Z https://community.nxp.com/t5/i-MX-Processors/iMX95-CA-bit-swapping/m-p/2133809#M239279 <P>Hi NXP,</P><P>Is bit swapping of the CA[6:0] pins allowed for the LPDDR5?</P><P>Apart from the mapping of the EVK, are there any successful bit mappings that can work for the iMX95?</P><P>Thanks,</P><P>Simon</P> Tue, 15 Jul 2025 06:38:59 GMT https://community.nxp.com/t5/i-MX-Processors/iMX95-CA-bit-swapping/m-p/2133809#M239279 simonng 2025-07-15T06:38:59Z https://community.nxp.com/t5/i-MX-Processors/iMX95-CA-bit-swapping/m-p/2137147#M239412 <P>Hi&nbsp;<a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/105311">@simonng</a>&nbsp;,</P> <P>As i.MX95 is still on propreduction, we do not have the hardware design supply. But from the previous product exprience, the&nbsp;<SPAN>&nbsp;CA[6:0] pins swapping are not support.</SPAN></P> <P><SPAN>Hope this can do help for you</SPAN></P> <P><SPAN>Wish you have a nice day</SPAN></P> <P><SPAN>Best Regards</SPAN></P> <P><SPAN>Rita</SPAN></P> Mon, 21 Jul 2025 07:52:21 GMT https://community.nxp.com/t5/i-MX-Processors/iMX95-CA-bit-swapping/m-p/2137147#M239412 Rita_Wang 2025-07-21T07:52:21Z