i.MX8MP MIPI-DSI panel integration difficulties

ntylerhw — Mon, 07 Jul 2025 12:58:08 GMT

Hello, I am looking for some guidance on integrating a MIPI-DSI display that does not have a dedicated driver at /drivers/gpu/drm/panel.

The display model is HT070BGEI30. Strangely there is nothing about this device online, but I attached the supplied datasheet. This panel looks like a 99% match to Feiyang FY07024DI26A30D - except these differences:
1) HT070BGEI30 has different MIPI commands (probably the Feiyang and HT070BGEI30 have different controller ICs?)
2) HT070BGEI30 MIPI clock + data lanes digital level is 3.3V, not 1.8V.

Because the datasheet matches the Feiyang FY07024DI26A30D very closely, I am attempting to use the driver at ‘/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c’, but with adapted MIPI commands (I manually changed lines 38-44 in panel-feiyang-fy07024di26a30d.c to match the HT070BGEI30 commands).

The adapted Feiyang driver was compiled into the kernel (thus integrating my changes to the MIPI commands). After compilation, driver kernel support was confirmed on the running target:
root@imx8mp-var-dart://proc# zcat /proc/config.gz | grep FEIYANG
CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=y

Device tree fragments:

&lcdif1 {
status = "okay";
};

&mipi_dsi {
status = "okay";

port@1 {
mipi_dsi_out: endpoint {
remote-endpoint = <&dsi_panel_in>;
};
};

panel {
compatible = "feiyang,fy07024di26a30d";
reg = <0>;
avdd-supply = <&reg_avdd>;
dvdd-supply = <&reg_dvdd>;
pinctrl-0 = <&pinctrl_mipi_panel>;
reset-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
status = "okay";

port {
dsi_panel_in: endpoint {
remote-endpoint = <&mipi_dsi_out>;
};
};
};
};

&iomuxc {

pinctrl_mipi_panel: mipipanelgrp {
fsl,pins = <
/* For pad control bitmask, see NXP document IMX8MPRM, Section 8.2.4.104 */
MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x5
>;
};
};

Results:
-> Black screen, no activity at all (apart from backlight on).
-> No activity observed on DSI CLK or DSI D0 lanes. All DSI CLK and data lanes all show a constant DC voltage of around 1.5v.
-> Panel reset GPIO normally high (as expected), but no falling edges to trigger panel reset are seen at boot up.
-> Kernel loads without failure messages, but dmesg shows issues with mpi_dsi and drm:

[ 0.064814] platform 32e60000.mipi_dsi: Fixed dependency cycle(s) with /soc@0/bus@32c00000/mipi_dsi@32e60000/panel
[ 0.064858] platform 32e60000.mipi_dsi: Fixed dependency cycle(s) with /soc@0/bus@32c00000/lcd-controller@32e80000
[ 0.065178] platform 32e60000.mipi_dsi: Fixed dependency cycle(s) with /soc@0/bus@32c00000/lcd-controller@32e80000
[ 0.065260] platform 32e80000.lcd-controller: Fixed dependency cycle(s) with /soc@0/bus@32c00000/mipi_dsi@32e60000
…
[ 1.476828] imx-drm display-subsystem: bound imx-lcdifv3-crtc.0 (ops lcdifv3_crtc_ops)
[ 1.484893] imx_sec_dsim_drv 32e60000.mipi_dsi: version number is 0x1060200
[ 1.492370] [drm:drm_bridge_attach] *ERROR* failed to attach bridge /soc@0/bus@32c00000/mipi_dsi@32e60000 to encoder DSI-34: -19
[ 1.503969] imx_sec_dsim_drv 32e60000.mipi_dsi: Failed to attach bridge: 32e60000.mipi_dsi
[ 1.512669] imx_sec_dsim_drv 32e60000.mipi_dsi: failed to bind sec dsim bridge: -517
…
[ 1.979211] [drm] Initialized vivante 1.0.0 20170808 for 40000000.mix_gpu_ml on minor 0
…
[ 2.320657] imx-drm display-subsystem: bound imx-lcdifv3-crtc.0 (ops lcdifv3_crtc_ops)
[ 2.328733] imx_sec_dsim_drv 32e60000.mipi_dsi: version number is 0x1060200
[ 2.336271] imx-drm display-subsystem: bound 32e60000.mipi_dsi (ops imx_sec_dsim_ops)
[ 2.344634] [drm] Initialized imx-drm 1.0.0 20120507 for display-subsystem on minor 1
[ 2.897564] imx_sec_dsim_drv 32e60000.mipi_dsi: wait pkthdr tx done time out
[ 2.897573] imx_sec_dsim_drv 32e60000.mipi_dsi: panel prepare failed: -16

Any ideas what's going wrong here? This is the first time i have done embedded linux bring up with a .dts file, so perhaps I'm missing something obvious?

Also, a second question about operating the panel as a 'generic' panel without dedicated driver. I am struggling to find any full examples of how to do this.

The panel supplier mentioned this:

“There is no need for a kernel driver, you just need DSI Init settings, all in the imx8mp .dts file:

MIPI CLK Speed:340Mbps(170MHZ)
H back porch:160
H front porch:160
H pulse width:10
V back porch:23
V front porch:12
V pulse width:1

MIPI command as following:
regw(0x80,0xAC);
regw(0x81,0xB8);
regw(0x82,0x09);
regw(0x83,0x78);
regw(0x84,0x7F);
regw(0x85,0xBB);
regw(0x86,0x70);
“

Is it really possible drive a MIPI-DSI Panel without a driver? What are they referring to here? I’m aware of the generic MIPI-DSI drivers and associated documentation in the linux-imx kernel, eg, panel-dsi-cm.c, panel-simple.c, etc. Is this what they are talking about?

Re: i.MX8MP MIPI-DSI panel integration difficulties

Bio_TICFSL — Mon, 07 Jul 2025 14:31:49 GMT

Hello,

The MIPI clock + data lanes pins are at 3.3V, on HT070BGEI30 you need 1.8v.

Regards

Re: i.MX8MP MIPI-DSI panel integration difficulties

ntylerhw — Mon, 07 Jul 2025 15:28:21 GMT

that is unfortunate. the datasheet states VDD=3.3v on page 7. I now see vdd=1.8v mentioned elsewhere on other tables. is it possible to change the MIPI voltages to 1.8v via the pin control registers?

also - about the second question - is the supplier talking about the generic drivers?

Re: i.MX8MP MIPI-DSI panel integration difficulties

ntylerhw — Tue, 08 Jul 2025 16:51:48 GMT

I dont think your statement about the MIPI clock and data lines is correct. Table 2 (D-PHY DC electrical specifications) of AN13573 (i.MX 8/RT MIPI DSI/CSI-2) states that V0h digital high level is 1.2V. Not 3v3.

https://www.nxp.com/docs/en/application-note/AN13573.pdf

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