topic Re: IMX8ULP LPDDR XJTAG Test in i.MX Processors

IMX8ULP LPDDR XJTAG Test

bajackson — Tue, 01 Jul 2025 15:38:40 GMT

Hello all,

I am trying to run an XJTAG test on the IMX8ULP for LPDDR. XJTAG is reporting errors for not being able to write to certain nets and the presence of shorts.

Looking at the reference manual for the IMX8 it states in section 75.5 that: "LPDDR need the following initialization procedure to be followed prior to enabling traffic to/from external DRAM." I have used the AID tool to initialize and calibrate the IMX8 for DDR and confirmed that it works outside of XJTAG testing.

If this initialization is needed to enable DDR traffic, then I am running in to the following issue: I use the tool to initialize and calibrate the DDR, but when I run the DDR test in XJTAG it resets the processor and the DDR configuration is lost and I fail the test since the IMX8 is no longer configured for DDR traffic.

If anyone has got XJTAG DDR test working on the IMX8 I would greatly appreciate any insight.

Thanks,

Re: IMX8ULP LPDDR XJTAG Test

JosephAtNXP — Wed, 02 Jul 2025 00:19:45 GMT

Hi,

Thank you for your interest in NXP Semiconductor products,

Make sure to follow the recommendations from the Hardware Developers Guide.

1. Assuming the use of a JTAG debugger, run the DDR initialization and open a debugger memory window pointing to the DDR memory map starting address.

You can also do this by the i.MX8ULP DDR Stress Test Tool.

2. Try writing a few words and verify that they can be read correctly.

3. If not, recheck the DDR initialization sequence and whether the DDR has been correctly soldered onto the board. Recheck the schematic to ensure that the DDR memory has been connected to the i.MX 8ULP correctly.

As well as making sure the sequence from page 5684 of i.MX 8 ULP Reference Manual.

Regards

Re: IMX8ULP LPDDR XJTAG Test

bajackson — Wed, 02 Jul 2025 15:33:24 GMT

Hello,

Thank you for your reply.

1. I am currently using the NXP IMX DDR Tool to set up the DDR.

2. I have confirmed that using this tool DDR communication is working outside of XJTAG

3. I assume you are referring to section 78.5 for XJTAG instruction initialization

The problem I seem to have is during XJTAG DDR tests there are functions (e.g. "SET") that puts the IMX8 into EXTEST mode which is resetting the IMX8. The reset is causing any DDR configuration to be lost.

My question at this point is: Do I need to follow the steps in section 75.5 of the reference manual to enable traffic for the DDR or is this just for calibrating DDR for normal high speed communication?

Thanks,

Re: IMX8ULP LPDDR XJTAG Test

JosephAtNXP — Wed, 02 Jul 2025 19:39:39 GMT

Hi,

It's for normal operation, you just need to follow the BSDL set up to get working with 8 ULP, will you be using DDR memory or DDR pins in your test?

Regards

Re: IMX8ULP LPDDR XJTAG Test

bajackson — Thu, 03 Jul 2025 15:17:21 GMT

I will be using both. I need to perform utilize boundary scan in XJTAG to find potential shorts and opens as well as perform tests that directly interface the memory of the DDR.

What do you mean by follow the BSDL set up?

Re: IMX8ULP LPDDR XJTAG Test

JosephAtNXP — Tue, 08 Jul 2025 03:13:16 GMT

page 5684