topic Re: imx93 ddr config in i.MX Processors

imx93 ddr config

jiangyaqiang — Mon, 23 Jun 2025 03:51:03 GMT

HI :

I have a 4G lpddr , which want to use in imx93 product , just use 2G of 4G only , is it possible ?

The ddr has 2Die and 2channel, and the config per die is :64Mx16DQx8banksx2channels

Row address=R0-R15

I use the config as bellow in " config tool for imx", but fail the pass the test.

I have attached the datasheet, could anyone tell me how to config it ?

Thanks and Best Regards

Re: imx93 ddr config

JorgeCas — Mon, 23 Jun 2025 20:21:49 GMT

Hello,

The SoC also supports dual rank single channel devices therefore, 16Gb/2GB density can be also achieved by using a dual rank single channel device with 16-row addresses (R0 - R15).

Since i.MX93 only supports 16-bit LPDDR4/X data bus, it can only interface with one of the channels and therefore, utilize only half of the device's density. When a device has 32Gb/4GB density however, only 16Gb/2GB can be used. There is no functional problem with using only one channel of a dual channel device as the channels are independent in LPDDR4/4X.

Best regards.

Re: imx93 ddr config

jiangyaqiang — Tue, 24 Jun 2025 03:26:34 GMT

HI JorgeCas:

Thanks for reply , it seems supported, but how to config it by "config tool for i.mx" ?

if choice 16Gb:1Gbx16, it use 17-row address, if use 8Gb:512Mbx16 and "number of rank=2" , it fail at "functional test"

Re: imx93 ddr config

JorgeCas — Tue, 24 Jun 2025 18:16:27 GMT

Hello,

Please share the log of failed test.

Best regards.

imx93 ddr config

jiangyaqiang — Wed, 25 Jun 2025 01:48:35 GMT

HI JorgeCas:

Here is the log(BTW: the test will pass if select ranks=1):

C:\nxp\i.MX_CFG_24.12\bin>prompt test-prefix :

test-prefix : "C:/nxp/i.MX_CFG_24.12/bin/python3/python" "C:/nxp/i.MX_CFG_24.12/bin/python3/memtool/memtool_entry.py" -t "runtest" -d "C:/ProgramData/NXP/mcu_data_24.12/processors/MIMX9332xxxxM/ksdk2_0/mem_validation/ddrc" -p "C:/Users/BERT~1.JIA/AppData/Local/Temp/mem_validation/phy_training_phy_test_0_0_.log" -l INFO "C:/Users/BERT~1.JIA/AppData/Local/Temp/mem_validation/connect.json" "C:/Users/BERT~1.JIA/AppData/Local/Temp/mem_validation/test.json" "C:/Users/BERT~1.JIA/AppData/Local/Temp/mem_validation/phy.json" "C:/Users/BERT~1.JIA/AppData/Local/Temp/mem_validation/ddrc_registers.json" "C:/Users/BERT~1.JIA/AppData/Local/Temp/mem_validation/ddrc_config.json" "C:/Users/BERT~1.JIA/AppData/Local/Temp/mem_validation/ddrc_config_in.json"

INFO memtool.utils.helper *****C:/Users/BERT~1.JIA/AppData/Local/Temp/mem_validation/connect.json

INFO memtool.utils.helper *****C:/Users/BERT~1.JIA/AppData/Local/Temp/mem_validation/test.json

INFO memtool.utils.helper *****C:/Users/BERT~1.JIA/AppData/Local/Temp/mem_validation/phy.json

INFO memtool.utils.helper *****C:/Users/BERT~1.JIA/AppData/Local/Temp/mem_validation/ddrc_registers.json

INFO memtool.utils.helper *****C:/Users/BERT~1.JIA/AppData/Local/Temp/mem_validation/ddrc_config.json

INFO memtool.utils.helper *****C:/Users/BERT~1.JIA/AppData/Local/Temp/mem_validation/ddrc_config_in.json

INFO memtool.processor.imx9.imx9_processor Xls mapping load time 0.013074

INFO memtool.processor.imx9.imx9_processor Config time 0.000998

INFO memtool.processor.imx9.imx9_processor DS file time 0.291115

INFO memtool.phyinit.phy_init Run phyinit for 2022.01\lpddr4x

INFO memtool.comm.serial_channel Using serial: COM4

INFO memtool.common.base_test Read app state WAIT_FOR_INPUT

INFO memtool.common.base_test Write app log level

INFO memtool.common.base_test Write app state CONFIG_RECEIVED

INFO test_app [INFO]: Execute Training Firmware for 1D pstate0@1866MHz...

INFO test_app [INFO]: Training Firmware completed for 1D pstate0@1866MHz with status 3; Execution ended in 0s.0ms.0us...

INFO test_app [INFO]: Get CDD registers for pstate 0...

INFO test_app [INFO]: Get trained CDD: g_cdd_rr_max[0] = 1, g_cdd_ww_max[0] = 0, g_cdd_rw_max[0] = 0, g_cdd_wr_max[0] = 0

INFO memtool.common.base_test Read phy status DDR PHY: 1D training failed

INFO root Number of logged items 0x8

ERROR memtool.common.base_test DDR PHY: 1D training failed

INFO memtool.common.base_test Read symbol app_state = 0x5588dcfe

INFO memtool.common.base_test Read symbol num_records = 0x0

INFO memtool.common.base_test App state WAIT_FOR_INPUT

INFO memtool.common.base_test Read symbol debug = [0, 0, 0, 0, 0, 0, 0, 0]

INFO memtool.common.base_test Read symbol err_capt_regs = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0]

INFO memtool.common.base_test Read symbol debug_regs = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]

{'phy_error_state': '3', 'app_state': 1435032830, 'num_records': 0, 'records': [], 'debug': '[0, 0, 0, 0, 0, 0, 0, 0]', 'err_capt_regs': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0]', 'debug_regs': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'}

****DONE****

Re: imx93 ddr config

JorgeCas — Thu, 26 Jun 2025 14:20:40 GMT

Hello,

It is good to know that can pass the test with 1 rank.

The log (DDR PHY: 1D training failed) could be caused by a mismatch between the memory topology and the settings in Config Tool. For that memory, you should use 1 rank and use only one channel.

Here more information regarding DDR guidelines for i.MX93:

i.MX 93 Memory Compatibility Guide - NXP Community

Best regards.

Re: imx93 ddr config

jiangyaqiang — Fri, 27 Jun 2025 08:19:50 GMT

HI JorgeCas:

From the linker you provide, it said that the chip sopport dual rank singe channel,

How to config this case (dual rank singe channel)?

Re: imx93 ddr config

JorgeCas — Fri, 27 Jun 2025 20:24:50 GMT

Hello,

Please export and share your current DDR config from the Config Tool.

Best regards.

Re: imx93 ddr config

jiangyaqiang — Mon, 30 Jun 2025 08:49:00 GMT

HI JorgeCas：

My ddr config generate by tool in the attachment, please check in.

Re: imx93 ddr config

jiangyaqiang — Mon, 30 Jun 2025 08:51:30 GMT

sorry ,missing attachemnt file

Re: imx93 ddr config

JorgeCas — Mon, 30 Jun 2025 18:30:38 GMT

Hello,

I checked this with internal team.

The Config Tool software has some predefined configurations for typical DDR configurations and cannot be customized to use that specific configuration since it is not implemented in the software to test it.

Unfortunately, it cannot be complete customized as happened with RPA tool for previous processors.

Best regards.