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    <title>i.MX ProcessorsのトピックRe: Dpram reading on m7core</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Dpram-reading-on-m7core/m-p/2114206#M238077</link>
    <description>Hello Team,&lt;BR /&gt;Any suggestion would be appreciated.&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;Thanks &amp;amp; regards,&lt;BR /&gt;adithya.</description>
    <pubDate>Wed, 11 Jun 2025 06:57:53 GMT</pubDate>
    <dc:creator>adithya369</dc:creator>
    <dc:date>2025-06-11T06:57:53Z</dc:date>
    <item>
      <title>Dpram reading on m7core</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Dpram-reading-on-m7core/m-p/2113744#M238048</link>
      <description>&lt;P&gt;Hi NXP support team,&lt;/P&gt;&lt;P&gt;I'm experiencing optimisation issues with reading DPRAM data on Verdin iMX8MP using the M7 core. Specifically, reading 40k locations takes around 300 milliseconds, while GPIO pin toggling takes 250 nanoseconds. With 16 address pins, 8 data pins, and 3 control pins, I'm struggling to achieve my target of reading 40k locations within 3 milliseconds. Can you provide guidance on optimizing the read performance or suggest alternative approaches to meet my requirements?&lt;/P&gt;</description>
      <pubDate>Tue, 10 Jun 2025 16:17:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Dpram-reading-on-m7core/m-p/2113744#M238048</guid>
      <dc:creator>adithya369</dc:creator>
      <dc:date>2025-06-10T16:17:01Z</dc:date>
    </item>
    <item>
      <title>Re: Dpram reading on m7core</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Dpram-reading-on-m7core/m-p/2114206#M238077</link>
      <description>Hello Team,&lt;BR /&gt;Any suggestion would be appreciated.&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;Thanks &amp;amp; regards,&lt;BR /&gt;adithya.</description>
      <pubDate>Wed, 11 Jun 2025 06:57:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Dpram-reading-on-m7core/m-p/2114206#M238077</guid>
      <dc:creator>adithya369</dc:creator>
      <dc:date>2025-06-11T06:57:53Z</dc:date>
    </item>
    <item>
      <title>Re: Dpram reading on m7core</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Dpram-reading-on-m7core/m-p/2114601#M238099</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;You can check with&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/5672"&gt;@toradex&lt;/a&gt;, but in general you can calibrate the DDR with this tool:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/DDR4-calibration-amp-configuration/td-p/1409012" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors/DDR4-calibration-amp-configuration/td-p/1409012&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;regards&lt;/P&gt;</description>
      <pubDate>Wed, 11 Jun 2025 16:16:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Dpram-reading-on-m7core/m-p/2114601#M238099</guid>
      <dc:creator>Bio_TICFSL</dc:creator>
      <dc:date>2025-06-11T16:16:06Z</dc:date>
    </item>
    <item>
      <title>Re: Dpram reading on m7core</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Dpram-reading-on-m7core/m-p/2115849#M238164</link>
      <description>Hello,&lt;BR /&gt;we want to place all code/data into TCM for the faster access. can you please provide me the linker script and also any relavant documentation to place the whole binary into TCM memory</description>
      <pubDate>Fri, 13 Jun 2025 06:03:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Dpram-reading-on-m7core/m-p/2115849#M238164</guid>
      <dc:creator>adithya369</dc:creator>
      <dc:date>2025-06-13T06:03:38Z</dc:date>
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