i.MX ProcessorsのトピックRe: GPIO R/W speed far below the set kCLOCK_RootIpg (133 Mhz)

GPIO R/W speed far below the set kCLOCK_RootIpg (133 Mhz)

Chengting — Sun, 19 Mar 2023 08:47:17 GMT

We'd plan to use GPIO4 for data transfer(i.MX8P dual core) . Thus we gave a test of the GPIO speed.

M7 part test.

//skipping the iomux setting and pin setting while (i<100 000 000) { //read GPIO_PinRead(GPIO4,0); //pulling high GPIO_PinWrite(GPIO4,18,1); //pulling low GPIO_PinWrite(GPIO4,18,0); i++; }

It cost 33 s, totally, the speed is far behind the IPG_clk we set, 133Mhz.

As the image show, every high last 65 ns, every repeat last 330 ns.

If the read cost 2 clock loop, the clock time is 30 ns, which is 33Mhz, far behind the 133 hHz in reference Manual.

Re: GPIO R/W speed far below the set kCLOCK_RootIpg (133 Mhz)

Sanket_Parekh — Wed, 22 Mar 2023 09:59:47 GMT

Hi @Chengting

I hope you are doing well.

The clock source for gpio modules is ipg_clk_s (Clock root: IPG_CLK_ROOT).

Here, ipg_clk_s is used for synchronization in gpio sampling, reading register values, etc...

It does not mean the frequency at which gpio output toggles in this example.

This test does have the overhead of other instructions (loop condition, increment,).

GPIO_PinWrite() function also contains various conditional branching.

Thanks & Regards

Sanket Parekh

Re: GPIO R/W speed far below the set kCLOCK_RootIpg (133 Mhz)

Chengting — Mon, 03 Apr 2023 10:31:14 GMT

Thanks for your reply. How do I know the correct speed (or the highest speed the platform can support)?

That's what I really really need. Thank you again.

static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin) { assert(pin < 32U); return (((base->DR) >> pin) & 0x1U); } void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output) { assert(pin < 32U); if (output == 0U) { #if (defined(FSL_FEATURE_IGPIO_HAS_DR_CLEAR) && FSL_FEATURE_IGPIO_HAS_DR_CLEAR) base->DR_CLEAR = (1UL << pin); #else base->DR &= ~(1UL << pin); /* Set pin output to low level.*/ //==> this branch #endif } else { #if (defined(FSL_FEATURE_IGPIO_HAS_DR_SET) && FSL_FEATURE_IGPIO_HAS_DR_SET) base->DR_SET = (1UL << pin); #else base->DR |= (1UL << pin); /* Set pin output to high level.*/ //==> this branch #endif } }

Re: GPIO R/W speed far below the set kCLOCK_RootIpg (133 Mhz)

Chengting — Tue, 04 Apr 2023 01:04:06 GMT

Thanks for your reply. How do I know the correct speed (or the highest speed the platform can support)?

That's what I really really need. Thank you again.

static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin)
{
    assert(pin < 32U);

    return (((base->DR) >> pin) & 0x1U);
}

void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output)
{
    assert(pin < 32U);
    if (output == 0U)
    {
#if (defined(FSL_FEATURE_IGPIO_HAS_DR_CLEAR) && FSL_FEATURE_IGPIO_HAS_DR_CLEAR)
        base->DR_CLEAR = (1UL << pin);
#else
        base->DR &= ~(1UL << pin); /* Set pin output to low level.*/ //==> this branch
#endif
    }
    else
    {
#if (defined(FSL_FEATURE_IGPIO_HAS_DR_SET) && FSL_FEATURE_IGPIO_HAS_DR_SET)
        base->DR_SET = (1UL << pin);
#else
        base->DR |= (1UL << pin);  /* Set pin output to high level.*/  //==> this branch
#endif
    }
}

Re: GPIO R/W speed far below the set kCLOCK_RootIpg (133 Mhz)

Sanket_Parekh — Thu, 06 Apr 2023 08:32:38 GMT

Hi @Chengting ,

I hope you are doing well.

The correct gpio togging speed is not documented anywhere as it depends upon many things and overheads of applications can also affect it.

Thanks & Regards,

Sanket Parekh

Re: GPIO R/W speed far below the set kCLOCK_RootIpg (133 Mhz)

adithya369 — Wed, 11 Jun 2025 06:55:50 GMT

Hi,
Do you got answer for this post??

Re: GPIO R/W speed far below the set kCLOCK_RootIpg (133 Mhz)

gidame — Wed, 11 Jun 2025 07:47:06 GMT

The person asking the question doesn't know what information to provide, such as pad settings and voltage. The person answering the question is not familiar with imx at all.
The datasheets of all imx chips have descriptions of IO AC characteristics.