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    <title>topic i.MX8m-mini DRAM Controller in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8m-mini-DRAM-Controller/m-p/2108272#M237804</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I followed the linux ref manual 2.5.4 and able to control the bus frequency, but it seems like not control the DRAM controller directly, correct?&lt;/P&gt;&lt;P&gt;If yes, what if I would like to control the DRAM Controller directly? Or I can do both at the same time?&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;P&gt;James Shih&lt;/P&gt;</description>
    <pubDate>Fri, 30 May 2025 21:55:29 GMT</pubDate>
    <dc:creator>JamesShih</dc:creator>
    <dc:date>2025-05-30T21:55:29Z</dc:date>
    <item>
      <title>i.MX8m-mini DRAM Controller</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8m-mini-DRAM-Controller/m-p/2108272#M237804</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I followed the linux ref manual 2.5.4 and able to control the bus frequency, but it seems like not control the DRAM controller directly, correct?&lt;/P&gt;&lt;P&gt;If yes, what if I would like to control the DRAM Controller directly? Or I can do both at the same time?&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;P&gt;James Shih&lt;/P&gt;</description>
      <pubDate>Fri, 30 May 2025 21:55:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8m-mini-DRAM-Controller/m-p/2108272#M237804</guid>
      <dc:creator>JamesShih</dc:creator>
      <dc:date>2025-05-30T21:55:29Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8m-mini DRAM Controller</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8m-mini-DRAM-Controller/m-p/2110212#M237878</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/250468"&gt;@JamesShih&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;What do you mean&amp;nbsp;&lt;SPAN&gt;control the DRAM Controller directly? please explain more details&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;B.R&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 04 Jun 2025 08:16:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8m-mini-DRAM-Controller/m-p/2110212#M237878</guid>
      <dc:creator>pengyong_zhang</dc:creator>
      <dc:date>2025-06-04T08:16:42Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8m-mini DRAM Controller</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8m-mini-DRAM-Controller/m-p/2110723#M237907</link>
      <description>Hi Pengyong,&lt;BR /&gt;&lt;BR /&gt;Sorry for the incomplete information, the DRAM Controller I mean is the DDR Controller.&lt;BR /&gt;&lt;BR /&gt;Right now in my environment, I'm able to use "busfreq" to set DDR and NOC to the lower frequency and for sure able to see the power consumption going down.&lt;BR /&gt;&lt;BR /&gt;Beside, there is another one called "devfreq", I tried to enable it in my environment, but unfortunately it didn't work and even not able to see the node.&lt;BR /&gt;&lt;BR /&gt;To clarify my question, I just want to confirm if in the same clock (lower frequency) condition by either busfreq or devfreq, from the power consumption point of view it shouldn't be any different, correct?&lt;BR /&gt;&lt;BR /&gt;Hopefully it's clear for you to understand my question, thanks.</description>
      <pubDate>Wed, 04 Jun 2025 21:34:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8m-mini-DRAM-Controller/m-p/2110723#M237907</guid>
      <dc:creator>JamesShih</dc:creator>
      <dc:date>2025-06-04T21:34:08Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8m-mini DRAM Controller</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8m-mini-DRAM-Controller/m-p/2111025#M237928</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/250468"&gt;@JamesShih&lt;/a&gt;&lt;/P&gt;
&lt;P&gt;NXP vendor tree is using a private busfreq [1] driver to do ddr and bus fabric scalling rather than using upstream ddrc &amp;amp; interconnect&lt;BR /&gt;driver which is still immature. And actually there's no i.MX driver users of ICC in current vendor kernel. So removing them in order to avoid confusing to customers&lt;/P&gt;
&lt;P&gt;B.R&lt;/P&gt;</description>
      <pubDate>Thu, 05 Jun 2025 07:03:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8m-mini-DRAM-Controller/m-p/2111025#M237928</guid>
      <dc:creator>pengyong_zhang</dc:creator>
      <dc:date>2025-06-05T07:03:56Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8m-mini DRAM Controller</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8m-mini-DRAM-Controller/m-p/2111483#M237945</link>
      <description>Thanks, it's clear for me now.</description>
      <pubDate>Thu, 05 Jun 2025 18:20:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8m-mini-DRAM-Controller/m-p/2111483#M237945</guid>
      <dc:creator>JamesShih</dc:creator>
      <dc:date>2025-06-05T18:20:23Z</dc:date>
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