https://community.nxp.com/t5/i-MX-Processors/i-MX-RT-1010-PowerOn-sequence/m-p/2106967#M237768 <P>I have a question about the PowerOn sequence of the i.MX RT 1010.</P><P>The Hardware Development Guide has Figure 1. Power up and power down sequence.<BR />Figure 1 does not show the maximum time for supplying DCDC_IN after supplying VDD_SNVS_IN and VDD_HIGH_IN.</P><P>Is there a time restriction between supplying VDD_SNVS_IN and VDD_HIGH_IN and supplying DCDC_IN?</P><P><LI-PRODUCT title="i.MX-RT1010" id="i.MX-RT1010"></LI-PRODUCT>&nbsp;</P> Thu, 29 May 2025 08:20:41 GMT yoshida_satoru 2025-05-29T08:20:41Z https://community.nxp.com/t5/i-MX-Processors/i-MX-RT-1010-PowerOn-sequence/m-p/2106967#M237768 <P>I have a question about the PowerOn sequence of the i.MX RT 1010.</P><P>The Hardware Development Guide has Figure 1. Power up and power down sequence.<BR />Figure 1 does not show the maximum time for supplying DCDC_IN after supplying VDD_SNVS_IN and VDD_HIGH_IN.</P><P>Is there a time restriction between supplying VDD_SNVS_IN and VDD_HIGH_IN and supplying DCDC_IN?</P><P><LI-PRODUCT title="i.MX-RT1010" id="i.MX-RT1010"></LI-PRODUCT>&nbsp;</P> Thu, 29 May 2025 08:20:41 GMT https://community.nxp.com/t5/i-MX-Processors/i-MX-RT-1010-PowerOn-sequence/m-p/2106967#M237768 yoshida_satoru 2025-05-29T08:20:41Z