topic How to Debug IMX6ULL DDR3 Timing in i.MX Processors

How to Debug IMX6ULL DDR3 Timing

Marlon — Tue, 20 May 2025 12:06:03 GMT

I have two sets of IMX6ULL PCBs—one designed by the manufacturer and the other designed by myself. Currently, I'm unsure how to debug the timing parameters (e.g., tCL, tRCD, tRP, tRC, ODT, ZQ, etc.) on my own PCB.

Is it possible to use an oscilloscope and DDR3 data logging to modify the DCD file?

The program is loaded into SRAM via imx_usb, and the DDR3 is initialized using the DCD configuration through imx_usb. The DCD settings are referenced from U-Boot.

IMAGE_VERSION 2
BOOT_FROM sd
DATA 4 0x020c4068 0xffffffff
DATA 4 0x020c406c 0xffffffff
DATA 4 0x020c4070 0xffffffff
.......................

Read memory in SRAM and verify if it matches the input

void test_ddr3()
{
UART1_SendString("\r\nDDR TEST\r\n");
for (int i = 0;i < 8;i++) {
ddr3_mem[i] = 0x12345678;
UART1_PrintHex32Ln(ddr3_mem[0]);
}
if (0x12345678 == ddr3_mem[0]) {
UART1_SendString("\r\nWell");
}
else {
UART1_SendString("\r\nBed!!!");
}
}

The following output is from the manufacturer's designed PCB:

DDR TEST
0x12345678
0x12345678
0x12345678
0x12345678
0x12345678
0x12345678
0x12345678
0x12345678
Well

The following output is from my own designed PCB:

DDR TEST
0xFFFFFFFF
0X0000FFFF
0xFF3CFF3C
0x0000FF00
0xFF00FF00
0X0000FF00
0xFF3DFF3D
0x0000FF00
0x00000432
Bed!!!

Any guidance would be greatly appreciated!

Re: How to Debug IMX6ULL DDR3 Timing

JorgeCas — Tue, 20 May 2025 18:15:59 GMT

Hello,

This parameter values are initial or target settings that are used before the DDR training performed in CPU side. During boot, the memory controller performs a calibration and adjusts these parameters according to the board conditions.

Even in the same design these values can vary since the conditions between the boards are not the same.

I suggest you perform a DDR stress test to generate the initialization/timing scripts according to your design.

Best regards.

Re: How to Debug IMX6ULL DDR3 Timing

Marlon — Tue, 10 Jun 2025 15:31:38 GMT

Currently, the DDR is operational, which was caused by the soldering issue.

Additionally, is the "DDR stress test" you mentioned referring to ddr_stress_tester_v3.00?

This program runs on Windows, and I hope to write a fully automated testing framework on Linux, aiming to incorporate the functionalities of ddr_stress_tester_v3.00.

Does the official source provide the source code?

ddr_stress_tester_v3.00 and the source code for the ddr-test-mx6ull.bin file.