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    <title>topic Re: i.MX6 Continuous BCLK in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253882#M23730</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&amp;nbsp; Please refer to section 22.5.1 (Continuous BCLK) of the i.MX6 SDL RM regarding operation&lt;/P&gt;&lt;P&gt;under continuous BCLK MODE.&amp;nbsp; BCLK is i.MX6 output clock.&amp;nbsp;&amp;nbsp; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;~Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 26 Nov 2014 05:48:09 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2014-11-26T05:48:09Z</dc:date>
    <item>
      <title>i.MX6 Continuous BCLK</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253873#M23721</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, if I follow the initialization flow for Continuous BCLK setting of EIM interface, does the BCLK output pin continues to produce clock even if the EIM access is not in synchronous mode? or&amp;nbsp; no EIM access at all. Because, there is a note written on page 996 of IMX6SDLRM.pdf that BCLK stops toggling when burst access is terminated.&lt;/P&gt;&lt;P&gt;The reason that I want the BCLK to be continuous at all time is because I want to use BCLK as a reference clock for FPGA. &lt;/P&gt;&lt;P&gt;Reference document, IMX6SDLRM.pdf,&amp;nbsp; i.MX 6Solo/6DualLite Applications Processor Reference Manual, Rev. 1, 04/2013. &lt;/P&gt;&lt;P&gt;Thanks. Rogelio&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Dec 2013 00:10:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253873#M23721</guid>
      <dc:creator>zeahr</dc:creator>
      <dc:date>2013-12-11T00:10:13Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 Continuous BCLK</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253874#M23722</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&amp;nbsp; Really there are two options to have a free-running EIM clock for cases, when the EIM is used to communicate with a FPGA. &lt;BR /&gt;To meet such requirement, the Continuous (non stop) BCLK feature (documented in the RM) was added and EIM_ACLK_FREERUN - as &lt;/P&gt;&lt;P&gt;an alternative. &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Dec 2013 04:42:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253874#M23722</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2013-12-11T04:42:51Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 Continuous BCLK</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253875#M23723</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Since&amp;nbsp; EIM_ACLK_FREERUN is an input pin, therefore the source clock is from FPGA (or from Oscillator) to i.MX6 for EIM communication?&lt;/P&gt;&lt;P&gt;If EIM_ACLK_FREERUN is used for FPGA communication, is BCLK not necessary duirng Burst Clock Mode (Synchronous Mode) access?&lt;/P&gt;&lt;P&gt;Thank you.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Dec 2013 09:55:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253875#M23723</guid>
      <dc:creator>zeahr</dc:creator>
      <dc:date>2013-12-11T09:55:16Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 Continuous BCLK</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253876#M23724</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;ACLK may be considered as input reference internal clock for the EIM.&lt;/P&gt;&lt;P&gt;BCLK may be considered as output clock for external synchronous devices.&lt;/P&gt;&lt;P&gt;Some external devices (as FPGA) requires continuous clock. Basically &lt;/P&gt;&lt;P&gt;this may be provided via CONT_BCLK_SEL bit in EIM_WCR.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 12 Dec 2013 07:25:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253876#M23724</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2013-12-12T07:25:18Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 Continuous BCLK</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253877#M23725</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I'm also trying to connect a FPGA to the i.MX6 processor, and I'm having same problem. However, our intention is to migrate at some point from Solo/DualLite to the i.MX6Dual. But, in a IMX6DQRM there is no such option as EIM_ACLK_FREERUN input pin. Is this feature supported on the Dual version or only on Solo/DualLite.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Also, I would appreciate some clarification on continous mode. So, BCLK can be in free running mode without EIM_ACLK_FREERUN pin used. But, if EIM_ACLK_FREERUN pin is used than internal EIM clock is synchronized to this clock using a DLL?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you.&lt;/P&gt;&lt;P&gt;Boris Snajder&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 12 Mar 2014 08:52:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253877#M23725</guid>
      <dc:creator>borissnajder</dc:creator>
      <dc:date>2014-03-12T08:52:09Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 Continuous BCLK</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253878#M23726</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Really the iMX6Q does NOT support continuous BCLK. &lt;/P&gt;&lt;P&gt;This is main difference between EIM module of the i.MX6 DQ and i.MX6 SDL.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 12 Mar 2014 10:38:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253878#M23726</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2014-03-12T10:38:52Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 Continuous BCLK</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253879#M23727</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please let me clear how to get a free-running EIM clock.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The Continuous BCLK is the only way for getting a free-running EIM clock, and the EIM_ACLK_FREERUN input pin can be used for EIM to run syncronus with the external device such as FPGA which needs reference clocks externally?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Nori Shinozaki&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 25 Nov 2014 12:33:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253879#M23727</guid>
      <dc:creator>norishinozaki</dc:creator>
      <dc:date>2014-11-25T12:33:10Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 Continuous BCLK</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253880#M23728</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;IMX6 DQ&amp;nbsp; &lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;does NOT support continuous BCLK. I mean we cannot guarantee&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;proper synchronization between internal (AXI) and external BCLK clocks, when &lt;BR /&gt;EIM_WCR[BCM] &lt;SPAN style="font-size: 10pt; line-height: 1.5em;"&gt;is set.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 10pt; line-height: 1.5em;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 10pt; line-height: 1.5em;"&gt;~Yuri.&lt;BR /&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 26 Nov 2014 04:39:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253880#M23728</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2014-11-26T04:39:41Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 Continuous BCLK</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253881#M23729</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt; Hello Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I wanted to hear about the case of iMX6 S/DL.&lt;/P&gt;&lt;P&gt;What's the case?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Nori Shinozaki&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 26 Nov 2014 04:43:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253881#M23729</guid>
      <dc:creator>norishinozaki</dc:creator>
      <dc:date>2014-11-26T04:43:03Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 Continuous BCLK</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253882#M23730</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&amp;nbsp; Please refer to section 22.5.1 (Continuous BCLK) of the i.MX6 SDL RM regarding operation&lt;/P&gt;&lt;P&gt;under continuous BCLK MODE.&amp;nbsp; BCLK is i.MX6 output clock.&amp;nbsp;&amp;nbsp; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;~Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 26 Nov 2014 05:48:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253882#M23730</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2014-11-26T05:48:09Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 Continuous BCLK</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253883#M23731</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The EIM_ACLK_FREERUN input can be used as internal EIM_ACLK?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;There are few descriptions on EIM_ACLK_FREERUN.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Nori Shinozaki&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 26 Nov 2014 07:05:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253883#M23731</guid>
      <dc:creator>norishinozaki</dc:creator>
      <dc:date>2014-11-26T07:05:01Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 Continuous BCLK</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253884#M23732</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;This is the reference. "AXI clock signal" is the only explanation.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/47587iD673684755B5E7F4/image-size/large?v=v2&amp;amp;px=999" title="pastedImage_0.png" alt="pastedImage_0.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 26 Nov 2014 09:22:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253884#M23732</guid>
      <dc:creator>norishinozaki</dc:creator>
      <dc:date>2014-11-26T09:22:59Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 Continuous BCLK</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253885#M23733</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; Basically, to meet requirements to have a free-running EIM clock for cases, &lt;/P&gt;&lt;P&gt;where customers used the EIM to communicate with an FPGA, design added &lt;BR /&gt;the Continuous BCLK feature and this EIM_ACLK_FREERUN as an alternative. &lt;/P&gt;&lt;P&gt;&amp;nbsp; But there is no more information and hardware specs about this signal.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;~Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 26 Nov 2014 09:54:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253885#M23733</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2014-11-26T09:54:09Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 Continuous BCLK</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253886#M23734</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;As you wrote EIM_ACLK_FREERUN as an alternative to Continous BCLK, it sounds like it's an output pin...&lt;/P&gt;&lt;P&gt;However in the RM...&lt;/P&gt;&lt;P&gt;Anyway the information is too few to use the pin whatever the funtion it is.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Nori Shinozaki&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 26 Nov 2014 10:08:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253886#M23734</guid>
      <dc:creator>norishinozaki</dc:creator>
      <dc:date>2014-11-26T10:08:33Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 Continuous BCLK</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253887#M23735</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;BLOCKQUOTE level="1"&gt;&lt;P&gt;Anyway the information is too few to use the pin whatever&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt; &amp;gt; the function it is.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Yes. this is what I want to say.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;~Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 26 Nov 2014 10:34:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253887#M23735</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2014-11-26T10:34:08Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 Continuous BCLK</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253888#M23736</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for answers.&lt;/P&gt;&lt;P&gt;Let's close this thread.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Nori Shinozaki&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 27 Nov 2014 08:51:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253888#M23736</guid>
      <dc:creator>norishinozaki</dc:creator>
      <dc:date>2014-11-27T08:51:58Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 Continuous BCLK</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253889#M23737</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is it possible to support the Continuous BCLK in i.MX6SoloLite?&lt;/P&gt;&lt;P&gt;(Should one set only CONT_BCLK_SEL bit in EIM_WCR?)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The external FPGA requires continuous clock, too. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Keita&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 07 Dec 2015 02:35:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253889#M23737</guid>
      <dc:creator>keitanagashima</dc:creator>
      <dc:date>2015-12-07T02:35:39Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 Continuous BCLK</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253890#M23738</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp; Yes, please refer to section 20.5.1 (Continuous BCLK) of the i.MX6 SL RM.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&lt;A href="http://cache.nxp.com/files/32bit/doc/ref_manual/IMX6SLRM.pdf" title="http://cache.nxp.com/files/32bit/doc/ref_manual/IMX6SLRM.pdf"&gt;http://cache.nxp.com/files/32bit/doc/ref_manual/IMX6SLRM.pdf&lt;/A&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 09 Dec 2015 05:09:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253890#M23738</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2015-12-09T05:09:01Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 Continuous BCLK</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253891#M23739</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hello.&lt;/P&gt;&lt;P&gt;Thank you for your reply. OK. I got it.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Keita&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 09 Dec 2015 05:36:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Continuous-BCLK/m-p/253891#M23739</guid>
      <dc:creator>keitanagashima</dc:creator>
      <dc:date>2015-12-09T05:36:59Z</dc:date>
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