https://community.nxp.com/t5/i-MX-Processors/Multicore-question-regarding-the-IMX1170/m-p/2095897#M237142 <P>Hi&nbsp;<a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/28770">@EdSutter</a>&nbsp;,</P> <P>Thank you so much for your interest in our products and for using our community.</P> <P>Yes, your understanding is correct.</P> <P><SPAN>There is no arbitration hardware on this SOC for any area of external memory (be it FlexSPI-NOR or SDRAM) that allows both cores to access the same memory block.</SPAN></P> <P><SPAN>The two cores must explicitly coordinate accesses to external memory through software-based synchronization.</SPAN></P> <P>Wish it helps you.&nbsp;</P> <P>Wish you a nice day!</P> <P>Best Regards<BR />MayLiu</P> Tue, 13 May 2025 02:18:00 GMT mayliu1 2025-05-13T02:18:00Z https://community.nxp.com/t5/i-MX-Processors/Multicore-question-regarding-the-IMX1170/m-p/2094762#M237102 <P>My application (currently working with MIMXRT1170EVKB and SDK_25_03_00) may eventually require that both the M7 and M4 cores be able to access (instruction and/or data) portions of memory that will be in FLEXSPI-Serial-NOR-Flash.&nbsp; The reason is simply that both cores may have more text/data/bss than there is internal RAM space.&nbsp; So I wanna make sure I know what I'm up against, here's my question...</P><P>It is 100% up to the two cores to coordinate this correct?&nbsp; In other words there is no arbitration hardware on this SOC for any area of external memory (be it FlexSPI-NOR or SDRAM) that allows both cores to access the same memory block...</P><P>True?</P><P>&nbsp;</P><P>&nbsp;</P> Fri, 09 May 2025 17:33:45 GMT https://community.nxp.com/t5/i-MX-Processors/Multicore-question-regarding-the-IMX1170/m-p/2094762#M237102 EdSutter 2025-05-09T17:33:45Z https://community.nxp.com/t5/i-MX-Processors/Multicore-question-regarding-the-IMX1170/m-p/2095897#M237142 <P>Hi&nbsp;<a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/28770">@EdSutter</a>&nbsp;,</P> <P>Thank you so much for your interest in our products and for using our community.</P> <P>Yes, your understanding is correct.</P> <P><SPAN>There is no arbitration hardware on this SOC for any area of external memory (be it FlexSPI-NOR or SDRAM) that allows both cores to access the same memory block.</SPAN></P> <P><SPAN>The two cores must explicitly coordinate accesses to external memory through software-based synchronization.</SPAN></P> <P>Wish it helps you.&nbsp;</P> <P>Wish you a nice day!</P> <P>Best Regards<BR />MayLiu</P> Tue, 13 May 2025 02:18:00 GMT https://community.nxp.com/t5/i-MX-Processors/Multicore-question-regarding-the-IMX1170/m-p/2095897#M237142 mayliu1 2025-05-13T02:18:00Z