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    <title>topic Re: i.mx6 PCIe Endpoint in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253673#M23678</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Past the wrong URL before by my phone, here is the correct one.&lt;/P&gt;&lt;P&gt;&lt;A _jive_internal="true" href="https://community.nxp.com/docs/DOC-95014"&gt;https://community.freescale.com/docs/DOC-95014&lt;/A&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 21 Jun 2013 16:43:02 GMT</pubDate>
    <dc:creator>richard_zhu</dc:creator>
    <dc:date>2013-06-21T16:43:02Z</dc:date>
    <item>
      <title>i.mx6 PCIe Endpoint</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253665#M23670</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;has anybody used the i.mx6 board as a PCIe endpoint?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I would like to connect the i.mx6 board to a host system. The host system acts as the PCIe root complex. As fas as I know, the official release contains only a rootcomplex driver.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is there source code available, which I could use as a starting basis to implement a PCIe endpoint?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks in advance.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 09 Feb 2013 18:31:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253665#M23670</guid>
      <dc:creator>test_me</dc:creator>
      <dc:date>2013-02-09T18:31:13Z</dc:date>
    </item>
    <item>
      <title>Re: i.mx6 PCIe Endpoint</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253666#M23671</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I try to solve a similar issue. Did you already get some additional information about this topic?&lt;/P&gt;&lt;P&gt;'Want to connect an iMX6 Board as endpoint to a Windows 7 PC as root complex.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you !&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 04 Mar 2013 13:48:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253666#M23671</guid>
      <dc:creator>dirkrohleder</dc:creator>
      <dc:date>2013-03-04T13:48:04Z</dc:date>
    </item>
    <item>
      <title>Re: i.mx6 PCIe Endpoint</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253667#M23672</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;At this point in time, Freescale is only supporting PCIe in root complex mode. Therefore, we do not have any End Point code to give out. I am aware the at least two customers of i.MX6 processors are using the i.MX6 in End Point mode. I do not know if they are willing to share their work, but this forum is the right place to ask for it.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Cheers,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Mark&lt;/P&gt;&lt;P&gt;&lt;SPAN class="mce_paste_marker"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 05 Mar 2013 08:04:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253667#M23672</guid>
      <dc:creator>YixingKong</dc:creator>
      <dc:date>2013-03-05T08:04:51Z</dc:date>
    </item>
    <item>
      <title>Re: i.mx6 PCIe Endpoint</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253668#M23673</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;P&gt;One pcie rc/ep validation had been done. One imx6q is used as pcie rc, the other one is used as pcie ep.&lt;/P&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 14 Jun 2013 16:00:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253668#M23673</guid>
      <dc:creator>richard_zhu</dc:creator>
      <dc:date>2013-06-14T16:00:04Z</dc:date>
    </item>
    <item>
      <title>Re: i.mx6 PCIe Endpoint</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253669#M23674</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;That is good news.&amp;nbsp; So does this mean Freescale will release some driver code soon to support iMX6 PCIe endpoint?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 14 Jun 2013 16:47:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253669#M23674</guid>
      <dc:creator>brettwilson</dc:creator>
      <dc:date>2013-06-14T16:47:32Z</dc:date>
    </item>
    <item>
      <title>Re: i.mx6 PCIe Endpoint</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253670#M23675</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;P&gt;Yes, it is.&lt;/P&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 14 Jun 2013 17:48:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253670#M23675</guid>
      <dc:creator>richard_zhu</dc:creator>
      <dc:date>2013-06-14T17:48:18Z</dc:date>
    </item>
    <item>
      <title>Re: i.mx6 PCIe Endpoint</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253671#M23676</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Excellent news!&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 10pt; line-height: 1.5em;"&gt;Is there an expected date available as to when this will be released, if at all? Additionally, is there any preliminary sample code available to show the endpoint setup?&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 20 Jun 2013 17:07:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253671#M23676</guid>
      <dc:creator>scottkanowitz</dc:creator>
      <dc:date>2013-06-20T17:07:33Z</dc:date>
    </item>
    <item>
      <title>Re: i.mx6 PCIe Endpoint</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253672#M23677</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I can past the patches into community, after I finish the usage how-to document.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 21 Jun 2013 06:39:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253672#M23677</guid>
      <dc:creator>richard_zhu</dc:creator>
      <dc:date>2013-06-21T06:39:23Z</dc:date>
    </item>
    <item>
      <title>Re: i.mx6 PCIe Endpoint</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253673#M23678</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Past the wrong URL before by my phone, here is the correct one.&lt;/P&gt;&lt;P&gt;&lt;A _jive_internal="true" href="https://community.nxp.com/docs/DOC-95014"&gt;https://community.freescale.com/docs/DOC-95014&lt;/A&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 21 Jun 2013 16:43:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253673#M23678</guid>
      <dc:creator>richard_zhu</dc:creator>
      <dc:date>2013-06-21T16:43:02Z</dc:date>
    </item>
    <item>
      <title>Re: i.mx6 PCIe Endpoint</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253674#M23679</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Does the RC supports MSI (Message Signaled Interrupts) in the existing release&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;regards&lt;/P&gt;&lt;P&gt;Salil&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 15 Aug 2013 11:32:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253674#M23679</guid>
      <dc:creator>salil</dc:creator>
      <dc:date>2013-08-15T11:32:56Z</dc:date>
    </item>
    <item>
      <title>Re: i.mx6 PCIe Endpoint</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253675#M23680</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;P&gt;&lt;SPAN style="font-size:14.0pt;mso-bidi-font-size:11.0pt"&gt;Yes, it is. MSI had been supported by the existing release.&lt;/SPAN&gt;&lt;/P&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 16 Aug 2013 01:41:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253675#M23680</guid>
      <dc:creator>richard_zhu</dc:creator>
      <dc:date>2013-08-16T01:41:16Z</dc:date>
    </item>
    <item>
      <title>Re: i.mx6 PCIe Endpoint</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253676#M23681</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Forgive me for repeating the question, wanted to confirm MSI support in freescale release L3.0.35_4.0.0_130424. I saw in the manual (i.MX 6Dual/6Quad Linux Reference Manual) accompanied with the release that MSI support is incomplete (see end note of section "35.1.4 Features"), copying exact lines:&lt;/P&gt;&lt;P&gt;" Out of the above, MSI, I/O access, Port Bus Driver integration are currently incomplete. "&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please confirm if this is true for this release or please indicate the exact release number in which MSI support became completely part of freescale release.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;regards&lt;/P&gt;&lt;P&gt;Salil&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 28 Aug 2013 07:47:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253676#M23681</guid>
      <dc:creator>salil</dc:creator>
      <dc:date>2013-08-28T07:47:50Z</dc:date>
    </item>
    <item>
      <title>Re: i.mx6 PCIe Endpoint</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253677#M23682</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;we have been able to use i.MX6 in PCIe EP mode connected to i.MX6 in PCIe RC and also to Freescale QorIQ P1020 running in RC mode. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In our case i.MX6 running in EP mode supports:&lt;/P&gt;&lt;P&gt;- inbound memory transactions (thru exposed BARs) and using iATU inbound translations to get from PCI bus address to a dedicated address in RAM&lt;/P&gt;&lt;P&gt;- outbound memory transactions to the RC or to other EPs&lt;/P&gt;&lt;P&gt;- generating MSI interrupts to the RC&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 02 Apr 2014 09:03:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253677#M23682</guid>
      <dc:creator>matevzlangus</dc:creator>
      <dc:date>2014-04-02T09:03:12Z</dc:date>
    </item>
    <item>
      <title>Re: i.mx6 PCIe Endpoint</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253678#M23683</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;That is a wonderful news. Is it possible to share the code (i.e. driver code of EP and RC used to configure above mentioned functionality ) running on iMX6 as EP and RC (or if it is P1020).&amp;nbsp; This would be of great help.&lt;/P&gt;&lt;P&gt;regards&lt;/P&gt;&lt;P&gt;Salil&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 02 Apr 2014 09:35:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253678#M23683</guid>
      <dc:creator>salil</dc:creator>
      <dc:date>2014-04-02T09:35:18Z</dc:date>
    </item>
    <item>
      <title>Re: i.mx6 PCIe Endpoint</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253679#M23684</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Matevz,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Will it be possible for you to share the endpoint code.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Haider&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 04 Sep 2014 11:38:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6-PCIe-Endpoint/m-p/253679#M23684</guid>
      <dc:creator>haider</dc:creator>
      <dc:date>2014-09-04T11:38:41Z</dc:date>
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