topic Configuration For DDR3L in i.MX Processors

Configuration For DDR3L

Sadatan123 — Fri, 25 Apr 2025 09:14:14 GMT

In DCD for IMX6Q the value of DRAM_SDCLK_0 is configured as below, will this work? Value of 18th bit (DDR_INPUT) is 0 which means it is CMOS input mode,

DCD_ENTRY (3, 0x020e0588, 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0

Do you think the value should be 0x00020030 instead of 0x00000030? or will this work?

Re: Configuration For DDR3L

JorgeCas — Fri, 25 Apr 2025 16:34:26 GMT

Hello,

The recommended value is 0x00000030.

uboot-imx/board/freescale/mx6sabresd/mx6sabresd.c at e3219a5a73445219df605d1492687918d488055c · nxp-imx/uboot-imx

Best regards.

Re: Configuration For DDR3L

Sadatan123 — Mon, 28 Apr 2025 12:01:13 GMT

So, what exactly this bit signifies, I am asking as we are configuring it CMOS when the clock is differential? Also, we are configuring GRP_DDRMODE as 0x00020000 which signifies as differential, although as per reference manual it impacts DRAM_DATA00- DRAM_DATA63 and these signals are all single ended.

Re: Configuration For DDR3L

JorgeCas — Mon, 28 Apr 2025 18:42:52 GMT

Hello,

The input mode parameter (DDR_INPUT bit) may be configured as CMOS or differential. This configures the voltage level at which the pins senses a transition from logic low to logic high and vice versa. In differential mode, the pins level transitions are at 50%. In CMOS input mode, the pins level transitions are at 80% for high and 20 % for low.

So, strictly speaking, this option should be set as CMOS for single-ended signals and as Differential for differential ones. But really different DDR_INPUT options may be used in case of timing problems in order to improve situation.

Best regards.

Re: Configuration For DDR3L

Sadatan123 — Sat, 10 May 2025 07:14:50 GMT

How can the DQS-D Delay time,CLK-ADD and CLK-DS be derived from DCD file, what will be the value if the configuration is as given below:

DCD_ENTRY(28, 0x021b0800, 0xA1390003) // DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.

// For target board, may need to run write levelling calibration to fine tune these settings.
DCD_ENTRY(29, 0x021b080c, 0x002D003A) // MMDC1_MPWLDECTRL0
DCD_ENTRY(30, 0x021b0810, 0x0038002B) // MMDC1_MPWLDECTRL1

//Read DQS Gating calibration
DCD_ENTRY(31, 0x021b083c, 0x03340338) // MPDGCTRL0 PHY0
DCD_ENTRY(32, 0x021b0840, 0x0334032C) // MPDGCTRL1 PHY0

//Read calibration
DCD_ENTRY(33, 0x021b0848, 0x4036383C) // MPRDDLCTL PHY0

//Write calibration
DCD_ENTRY(34, 0x021b0850, 0x2E384038) // MPWRDLCTL PHY0

//read data bit delay: (3 is the recommended default value, although out of reset value is 0)
DCD_ENTRY(35, 0x021b081c, 0x33333333) // DDR_PHY_P0_MPREDQBY0DL3
DCD_ENTRY(36, 0x021b0820, 0x33333333) // DDR_PHY_P0_MPREDQBY1DL3
DCD_ENTRY(37, 0x021b0824, 0x33333333) // DDR_PHY_P0_MPREDQBY2DL3
DCD_ENTRY(38, 0x021b0828, 0x33333333) // DDR_PHY_P0_MPREDQBY3DL3

// Complete calibration by forced measurement:
DCD_ENTRY(39, 0x021b08b8, 0x00000800) // DDR_PHY_P0_MPMUR0, frc_msr
//=============================================================================
// Calibration setup end
//=============================================================================

//MMDC init:
DCD_ENTRY(40, 0x021b0004, 0x00020036) // MMDC0_MDPDC
DCD_ENTRY(41, 0x021b0008, 0x09444040) // MMDC0_MDOTC
DCD_ENTRY(42, 0x021b000c, 0xB8BE7955) // MMDC0_MDCFG0
DCD_ENTRY(43, 0x021b0010, 0xFF328F64) // MMDC0_MDCFG1
DCD_ENTRY(44, 0x021b0014, 0x01FF00DB) // MMDC0_MDCFG2

//MDMISC: RALAT kept to the high level of 5.
//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
//b. Small performance improvement
DCD_ENTRY(45, 0x021b0018, 0x00011740) // MMDC0_MDMISC
DCD_ENTRY(46, 0x021b001c, 0x00008000) // MMDC0_MDSCR, set the Configuration request bit during MMDC set up
DCD_ENTRY(47, 0x021b002c, 0x000026D2) // MMDC0_MDRWD
DCD_ENTRY(48, 0x021b0030, 0x00BE1023) // MMDC0_MDOR
DCD_ENTRY(49, 0x021b0040, 0x00000047) // Chan0 CS0_END
DCD_ENTRY(50, 0x021b0000, 0x85190000) // MMDC0_MDCTL

//Mode register writes
DCD_ENTRY(51, 0x021b001c, 0x00888032) // MMDC0_MDSCR, MR2 write, CS0
DCD_ENTRY(52, 0x021b001c, 0x00008033) // MMDC0_MDSCR, MR3 write, CS0
DCD_ENTRY(53, 0x021b001c, 0x00008031) // MMDC0_MDSCR, MR1 write, CS0
DCD_ENTRY(54, 0x021b001c, 0x19408030) // MMDC0_MDSCR, MR0write, CS0
DCD_ENTRY(55, 0x021b001c, 0x04008040) // MMDC0_MDSCR, ZQ calibration command sent to device on CS0