topic iMX8MN M7 Core SDMA Question in i.MX Processors

iMX8MN M7 Core SDMA Question

jaredwheeler — Thu, 20 Mar 2025 01:30:03 GMT

Quick question about using the SDMA from the 8M Nano's M7 core.

I want to perform simultaneous and asynchronous DMA data transfers on the ECSPI and SAI interfaces from the Cortex M7 domain. I'm having trouble getting this to work.

It involves using both the SDMAARM1 and the SDMAARM3 instances at the same time. Is there anyone who can quickly tell me if this should be possible? Is the system designed such that multiple DMA instances can work in parallel?

I do have the ECSPI2/DMA1 transfer, and the SAI3/DMA3 transfer working fine individually. However when I attempt a SPI DMA transfer while the SAI DMA is running, the SPI DMA reports busy and never sends any data.

Any insight here would be appreciated!

Re: iMX8MN M7 Core SDMA Question

Rita_Wang — Thu, 20 Mar 2025 07:48:25 GMT

In RDC settings, The SDMA1 is not assigned to M7 core.
In ATF settings, the RDC peripheral write permission is not enabled.

So please try the following modify:
In the the following, the item 1 is resolved by adding a Peripheral_RdcSetting function, in which the SDMA1 is assigned to M7 core:

RDC_SetMasterDomainAssignment(RDC, kRDC_Master_SDMA1_PERIPH, &assignment);
RDC_SetMasterDomainAssignment(RDC, kRDC_Master_SDMA1_BURST, &assignment);
RDC_SetMasterDomainAssignment(RDC, kRDC_Master_SDMA1_SPBA1, &assignment);

Moreover, the RDC peripheral write permission need to be enabled in ATF:

Patch:

diff --git a/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c
index 1c03ed16c..7f99df861 100644
--- a/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c
@@ -110,7 +110,7 @@ static const struct imx_rdc_cfg rdc[] = {
/* peripherals domain permission */
RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W),
RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W),
- RDC_PDAPn(RDC_PDAP_RDC, D0R | D0W | D1R),
+ RDC_PDAPn(RDC_PDAP_RDC, D0R | D0W | D1R | D1W),

/* memory region */
RDC_MEM_REGIONn(16, 0x0, 0x0, 0xff),

And for a test, user can just modify the register in u-boot with command：

mw 0x303d0474 0x0000000f

Re: iMX8MN M7 Core SDMA Question

spthx — Wed, 26 Mar 2025 02:43:34 GMT

If you are using the mcux-sdk SDMA driver and using the same channel (e.g. channel1) for SDMA1 and SDMA3, this may be due to a bug in the SDMA driver.

On the A53, but I have encountered similar problems when trying to run UART4 and SAI3 on SDMA1 and SDMA3 respectively.
The problem was avoided by modifying s_SDMACCB[0][handle->channel] in SDMA_HandleIRQ to s_SDMACCB[instance][handle->channel].
It could also be avoided by using different channels (e.g. SDMA1 for channel 1, SDMA3 for channel 2).

Regards,