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<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX Processorsのトピックimx8mp clock configuration for MIPI CSI2</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-clock-configuration-for-MIPI-CSI2/m-p/2054169#M234621</link>
    <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I am working on imx8mp PhyTec SoM module and connected a LVDS to MIPI bridge on CSI0 with a 2-lane configuration. The bridge is generating a test pattern and I am trying to understand on how to configure the clocks for this configuration.&lt;BR /&gt;I am able to capture the image from the camera, but it is not coming out to be right.&lt;BR /&gt;Below is the DTS configuration that I have been trying.&lt;BR /&gt;The commented lines, is everything I have tried so far.&lt;BR /&gt;The I2C of the bridge is working properly and I get debug output from it.&lt;BR /&gt;The bridge is using a pixel clock frequency of 74.25 MHz. It has been configured with&amp;nbsp;1920x1080 at 60Hz&amp;nbsp;&amp;nbsp;signal.&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;Total&amp;nbsp;Pixels&amp;nbsp;Per&amp;nbsp;Second&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class=""&gt;=&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;1920&lt;/SPAN&gt;&lt;SPAN class=""&gt;×&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;1080&lt;/SPAN&gt;&lt;SPAN class=""&gt;×&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;60&lt;/SPAN&gt;&lt;SPAN class=""&gt;=&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;124&lt;/SPAN&gt;&lt;SPAN class=""&gt;,&lt;/SPAN&gt;&lt;SPAN class=""&gt;416&lt;/SPAN&gt;&lt;SPAN class=""&gt;,&lt;/SPAN&gt;&lt;SPAN class=""&gt;000&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;Data&amp;nbsp;Rate&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class=""&gt;=&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;74.25&lt;/SPAN&gt;&lt;SPAN class=""&gt;×&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;1&lt;/SPAN&gt;&lt;SPAN class=""&gt;0&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;6&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class=""&gt;×&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;24&lt;/SPAN&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;bits&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt; &lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;=1.782&amp;nbsp;Gbps&amp;nbsp;(total).&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;For two lanes it will be 891 Mbps.&lt;BR /&gt;And since DDR operates at twice rate, the clock frequency for MIPI will be 445.5 MHz.&lt;BR /&gt;&lt;BR /&gt;Hence I tried configuring link-frequencies / clock-frequency to multiple of such values. However I don't get the right image.&lt;BR /&gt;&lt;BR /&gt;In the kernel logs, I see the error:&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;LI-CODE lang="markup"&gt;[  472.546870] mxc-mipi-csi2.0: Frame End events: 3
[  472.551485] mxc-mipi-csi2.0: Frame Start events: 235
[  472.556446] mxc-mipi-csi2.0: Non-image data after odd frame events: 0
[  472.562882] mxc-mipi-csi2.0: Non-image data before odd frame events: 0
[  472.569406] mxc-mipi-csi2.0: Non-image data after even frame events: 0
[  472.575930] mxc-mipi-csi2.0: Non-image data before even frame events: 0
[  472.582540] mxc-mipi-csi2.0: Unknown Error events: 1277
[  472.587762] mxc-mipi-csi2.0: CRC Error events: 87
[  472.592464] mxc-mipi-csi2.0: ECC Error events: 43758
[  472.597425] mxc-mipi-csi2.0: FIFO Overflow Error events: 0
[  472.602907] mxc-mipi-csi2.0: Lost Frame End Error events: 231
[  472.608651] mxc-mipi-csi2.0: Lost Frame Start Error events: 3
[  472.614393] mxc-mipi-csi2.0: SOT Error events: 40031&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;My question is:&lt;BR /&gt;1. Am I missing anything in clock configuration?&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;2. Is there anything in ISI block, that I need to configuration?&lt;BR /&gt;3. Should there be anything else I should be concerned about? Any other parameters?&lt;BR /&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;DTS configuration:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;LI-CODE lang="markup"&gt;&amp;amp;cameradev {    
  status = "okay";    
        cap_device {    
               status = "okay";    
        };    
 };    
     
 &amp;amp;i2c3 {    
     status = "okay";    
         
     lvds_bridge {    
        reg = &amp;lt;0x5A&amp;gt;;    
        status = "okay";    
        compatible = "lt9211c";    
        #address-cells = &amp;lt;0x1&amp;gt;;    
        #size-cells = &amp;lt;0x0&amp;gt;;    
        //mclk = &amp;lt;24000000&amp;gt;;    
        //mclk_source = &amp;lt;0&amp;gt;;    
        //mipi-csi;    
         
        port {    
         lt9211c_ep: endpoint {    
          data-lanes = &amp;lt;1 2&amp;gt;;    
          clock-lanes = &amp;lt;0&amp;gt;;    
          bus-type = &amp;lt;4&amp;gt;;    
          clock-noncontinuous = &amp;lt;1&amp;gt;;    
          //link-frequencies = /bits/ 64 &amp;lt;450000000&amp;gt;;    
          remote-endpoint = &amp;lt;&amp;amp;mipi_csi0_ep&amp;gt;;    
          clock-frequency = &amp;lt;74250000&amp;gt;; // Pixel clock in Hz (74.25 MHz)     
          hsync-active = &amp;lt;0&amp;gt;;  // Sync polarity    
          vsync-active = &amp;lt;0&amp;gt;;           
          pclk-sample = &amp;lt;1&amp;gt;;   // Sample on rising edge    
         };                              
        };                                
                                          
     };                                                                                                                                                                                      
 };                                        
 
 &amp;amp;isi_0 {    
       status = "okay";    
        cap_device {
               status = "okay";
        };
        m2m_device {
         status = "disabled";
        };
 };
 
 &amp;amp;isi_1 {
         status = "disabled";
         cap_device {
                status = "okay";
         };
 };
 
 &amp;amp;mipi_csi_0 {
  status = "okay";
   #address-cells = &amp;lt;1&amp;gt;;
  #size-cells = &amp;lt;0&amp;gt;;
  
   //assigned-clocks = &amp;lt;&amp;amp;clk IMX8MP_CLK_MEDIA_CAM2_PIX&amp;gt;;
   //assigned-clock-parents = &amp;lt;&amp;amp;clk IMX8MP_SYS_PLL2_1000M&amp;gt;;
   //assigned-clock-rates = &amp;lt;500000000&amp;gt;;
   // clock-frequency = &amp;lt;500000000&amp;gt;;
   clock-frequency = &amp;lt;74250000&amp;gt;; // 74.25 MHz
   //max-pixel-frequency = /bits/ 64 &amp;lt;266000000&amp;gt;;
   //link-frequencies = /bits/ 64 &amp;lt;505500000&amp;gt;;
   //max-lane-frequency = /bits/ 64 &amp;lt;750000000&amp;gt;;
   //max-data-rate = /bits/ 64 &amp;lt;0&amp;gt;;
   //link-frequencies = /bits/ 64 &amp;lt;750000000&amp;gt;;
   //max-lane-frequency = /bits/ 64 &amp;lt;750000000&amp;gt;;
   //max-pixel-frequency = /bits/ 64 &amp;lt;266000000&amp;gt;;
   //max-data-rate = /bits/ 64 &amp;lt;0&amp;gt;;
   //link-frequencies = /bits/ 64 &amp;lt;505500000&amp;gt;;
   //clock-frequency = &amp;lt;505500000&amp;gt;;
  
   //link-frequencies = /bits/ 64 &amp;lt;1011000000&amp;gt;;
  //clock-frequency = &amp;lt;1011000000&amp;gt;;
  
   port@0 {
   reg = &amp;lt;0&amp;gt;;
   mipi_csi0_ep: endpoint {
    remote-endpoint = &amp;lt;&amp;amp;lt9211c_ep&amp;gt;;
     data-lanes = &amp;lt;2&amp;gt;;
     csis-hs-settle = &amp;lt;4&amp;gt;;
     csis-clk-settle = &amp;lt;2&amp;gt;;
     csis-wclk;
     bus-type = &amp;lt;4&amp;gt;;  /* 4 = MIPI CSI-2 D-PHY */
     //mclk = &amp;lt;24000000&amp;gt;;
     //mclk_source = &amp;lt;0&amp;gt;;
     //mclk = &amp;lt;74_250000&amp;gt;; // Pixel clock in Hz (74250 kHz)
     //link-frequencies = /bits/ 64 &amp;lt;505500000&amp;gt;; // Mentioned in the LT9211 datasheet
     //max-pixelrate = &amp;lt;74250000&amp;gt;; // Mentioned in the LT9211 datasheet
    };
  };
 };
 
 &amp;amp;mipi_csi_1 {
  status = "disabled";
   #address-cells = &amp;lt;1&amp;gt;;
  #size-cells = &amp;lt;0&amp;gt;;
  port@0 {
   reg = &amp;lt;1&amp;gt;;
   mipi_csi1_ep: endpoint {};
  };
 };
 &lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Captured image:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="frame.png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/326357i5D3D1B2610A13F07/image-size/large?v=v2&amp;amp;px=999" role="button" title="frame.png" alt="frame.png" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;frame.png&lt;/span&gt;&lt;/span&gt;&lt;/P&gt;</description>
    <pubDate>Sun, 02 Mar 2025 09:30:07 GMT</pubDate>
    <dc:creator>rajtend</dc:creator>
    <dc:date>2025-03-02T09:30:07Z</dc:date>
    <item>
      <title>imx8mp clock configuration for MIPI CSI2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-clock-configuration-for-MIPI-CSI2/m-p/2054169#M234621</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I am working on imx8mp PhyTec SoM module and connected a LVDS to MIPI bridge on CSI0 with a 2-lane configuration. The bridge is generating a test pattern and I am trying to understand on how to configure the clocks for this configuration.&lt;BR /&gt;I am able to capture the image from the camera, but it is not coming out to be right.&lt;BR /&gt;Below is the DTS configuration that I have been trying.&lt;BR /&gt;The commented lines, is everything I have tried so far.&lt;BR /&gt;The I2C of the bridge is working properly and I get debug output from it.&lt;BR /&gt;The bridge is using a pixel clock frequency of 74.25 MHz. It has been configured with&amp;nbsp;1920x1080 at 60Hz&amp;nbsp;&amp;nbsp;signal.&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;Total&amp;nbsp;Pixels&amp;nbsp;Per&amp;nbsp;Second&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class=""&gt;=&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;1920&lt;/SPAN&gt;&lt;SPAN class=""&gt;×&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;1080&lt;/SPAN&gt;&lt;SPAN class=""&gt;×&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;60&lt;/SPAN&gt;&lt;SPAN class=""&gt;=&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;124&lt;/SPAN&gt;&lt;SPAN class=""&gt;,&lt;/SPAN&gt;&lt;SPAN class=""&gt;416&lt;/SPAN&gt;&lt;SPAN class=""&gt;,&lt;/SPAN&gt;&lt;SPAN class=""&gt;000&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;Data&amp;nbsp;Rate&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class=""&gt;=&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;74.25&lt;/SPAN&gt;&lt;SPAN class=""&gt;×&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;1&lt;/SPAN&gt;&lt;SPAN class=""&gt;0&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;6&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class=""&gt;×&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;24&lt;/SPAN&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;bits&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt; &lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;=1.782&amp;nbsp;Gbps&amp;nbsp;(total).&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;For two lanes it will be 891 Mbps.&lt;BR /&gt;And since DDR operates at twice rate, the clock frequency for MIPI will be 445.5 MHz.&lt;BR /&gt;&lt;BR /&gt;Hence I tried configuring link-frequencies / clock-frequency to multiple of such values. However I don't get the right image.&lt;BR /&gt;&lt;BR /&gt;In the kernel logs, I see the error:&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;LI-CODE lang="markup"&gt;[  472.546870] mxc-mipi-csi2.0: Frame End events: 3
[  472.551485] mxc-mipi-csi2.0: Frame Start events: 235
[  472.556446] mxc-mipi-csi2.0: Non-image data after odd frame events: 0
[  472.562882] mxc-mipi-csi2.0: Non-image data before odd frame events: 0
[  472.569406] mxc-mipi-csi2.0: Non-image data after even frame events: 0
[  472.575930] mxc-mipi-csi2.0: Non-image data before even frame events: 0
[  472.582540] mxc-mipi-csi2.0: Unknown Error events: 1277
[  472.587762] mxc-mipi-csi2.0: CRC Error events: 87
[  472.592464] mxc-mipi-csi2.0: ECC Error events: 43758
[  472.597425] mxc-mipi-csi2.0: FIFO Overflow Error events: 0
[  472.602907] mxc-mipi-csi2.0: Lost Frame End Error events: 231
[  472.608651] mxc-mipi-csi2.0: Lost Frame Start Error events: 3
[  472.614393] mxc-mipi-csi2.0: SOT Error events: 40031&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;My question is:&lt;BR /&gt;1. Am I missing anything in clock configuration?&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;2. Is there anything in ISI block, that I need to configuration?&lt;BR /&gt;3. Should there be anything else I should be concerned about? Any other parameters?&lt;BR /&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;DTS configuration:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;LI-CODE lang="markup"&gt;&amp;amp;cameradev {    
  status = "okay";    
        cap_device {    
               status = "okay";    
        };    
 };    
     
 &amp;amp;i2c3 {    
     status = "okay";    
         
     lvds_bridge {    
        reg = &amp;lt;0x5A&amp;gt;;    
        status = "okay";    
        compatible = "lt9211c";    
        #address-cells = &amp;lt;0x1&amp;gt;;    
        #size-cells = &amp;lt;0x0&amp;gt;;    
        //mclk = &amp;lt;24000000&amp;gt;;    
        //mclk_source = &amp;lt;0&amp;gt;;    
        //mipi-csi;    
         
        port {    
         lt9211c_ep: endpoint {    
          data-lanes = &amp;lt;1 2&amp;gt;;    
          clock-lanes = &amp;lt;0&amp;gt;;    
          bus-type = &amp;lt;4&amp;gt;;    
          clock-noncontinuous = &amp;lt;1&amp;gt;;    
          //link-frequencies = /bits/ 64 &amp;lt;450000000&amp;gt;;    
          remote-endpoint = &amp;lt;&amp;amp;mipi_csi0_ep&amp;gt;;    
          clock-frequency = &amp;lt;74250000&amp;gt;; // Pixel clock in Hz (74.25 MHz)     
          hsync-active = &amp;lt;0&amp;gt;;  // Sync polarity    
          vsync-active = &amp;lt;0&amp;gt;;           
          pclk-sample = &amp;lt;1&amp;gt;;   // Sample on rising edge    
         };                              
        };                                
                                          
     };                                                                                                                                                                                      
 };                                        
 
 &amp;amp;isi_0 {    
       status = "okay";    
        cap_device {
               status = "okay";
        };
        m2m_device {
         status = "disabled";
        };
 };
 
 &amp;amp;isi_1 {
         status = "disabled";
         cap_device {
                status = "okay";
         };
 };
 
 &amp;amp;mipi_csi_0 {
  status = "okay";
   #address-cells = &amp;lt;1&amp;gt;;
  #size-cells = &amp;lt;0&amp;gt;;
  
   //assigned-clocks = &amp;lt;&amp;amp;clk IMX8MP_CLK_MEDIA_CAM2_PIX&amp;gt;;
   //assigned-clock-parents = &amp;lt;&amp;amp;clk IMX8MP_SYS_PLL2_1000M&amp;gt;;
   //assigned-clock-rates = &amp;lt;500000000&amp;gt;;
   // clock-frequency = &amp;lt;500000000&amp;gt;;
   clock-frequency = &amp;lt;74250000&amp;gt;; // 74.25 MHz
   //max-pixel-frequency = /bits/ 64 &amp;lt;266000000&amp;gt;;
   //link-frequencies = /bits/ 64 &amp;lt;505500000&amp;gt;;
   //max-lane-frequency = /bits/ 64 &amp;lt;750000000&amp;gt;;
   //max-data-rate = /bits/ 64 &amp;lt;0&amp;gt;;
   //link-frequencies = /bits/ 64 &amp;lt;750000000&amp;gt;;
   //max-lane-frequency = /bits/ 64 &amp;lt;750000000&amp;gt;;
   //max-pixel-frequency = /bits/ 64 &amp;lt;266000000&amp;gt;;
   //max-data-rate = /bits/ 64 &amp;lt;0&amp;gt;;
   //link-frequencies = /bits/ 64 &amp;lt;505500000&amp;gt;;
   //clock-frequency = &amp;lt;505500000&amp;gt;;
  
   //link-frequencies = /bits/ 64 &amp;lt;1011000000&amp;gt;;
  //clock-frequency = &amp;lt;1011000000&amp;gt;;
  
   port@0 {
   reg = &amp;lt;0&amp;gt;;
   mipi_csi0_ep: endpoint {
    remote-endpoint = &amp;lt;&amp;amp;lt9211c_ep&amp;gt;;
     data-lanes = &amp;lt;2&amp;gt;;
     csis-hs-settle = &amp;lt;4&amp;gt;;
     csis-clk-settle = &amp;lt;2&amp;gt;;
     csis-wclk;
     bus-type = &amp;lt;4&amp;gt;;  /* 4 = MIPI CSI-2 D-PHY */
     //mclk = &amp;lt;24000000&amp;gt;;
     //mclk_source = &amp;lt;0&amp;gt;;
     //mclk = &amp;lt;74_250000&amp;gt;; // Pixel clock in Hz (74250 kHz)
     //link-frequencies = /bits/ 64 &amp;lt;505500000&amp;gt;; // Mentioned in the LT9211 datasheet
     //max-pixelrate = &amp;lt;74250000&amp;gt;; // Mentioned in the LT9211 datasheet
    };
  };
 };
 
 &amp;amp;mipi_csi_1 {
  status = "disabled";
   #address-cells = &amp;lt;1&amp;gt;;
  #size-cells = &amp;lt;0&amp;gt;;
  port@0 {
   reg = &amp;lt;1&amp;gt;;
   mipi_csi1_ep: endpoint {};
  };
 };
 &lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Captured image:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="frame.png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/326357i5D3D1B2610A13F07/image-size/large?v=v2&amp;amp;px=999" role="button" title="frame.png" alt="frame.png" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;frame.png&lt;/span&gt;&lt;/span&gt;&lt;/P&gt;</description>
      <pubDate>Sun, 02 Mar 2025 09:30:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8mp-clock-configuration-for-MIPI-CSI2/m-p/2054169#M234621</guid>
      <dc:creator>rajtend</dc:creator>
      <dc:date>2025-03-02T09:30:07Z</dc:date>
    </item>
    <item>
      <title>Re: imx8mp clock configuration for MIPI CSI2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-clock-configuration-for-MIPI-CSI2/m-p/2054172#M234622</link>
      <description>&lt;P&gt;I am using following commands to capture the image:&lt;/P&gt;&lt;LI-CODE lang="markup"&gt;root@phyboard-pollux-imx8mp-3:~# v4l2-ctl -d /dev/video0 --set-fmt-video=width=1920,height=1080,pixelformat=RGB3
root@phyboard-pollux-imx8mp-3:~# v4l2-ctl --device /dev/video0 --stream-mmap --stream-count=1 --stream-to=frame.raw&lt;/LI-CODE&gt;&lt;P&gt;And then I use FFMPEG to convert it to other format. FFMPEG throws an error:&lt;/P&gt;&lt;LI-CODE lang="markup"&gt;ffmpeg -f rawvideo -pix_fmt rgb24 -s 1920x1080 -i frame.raw -frames:v 1 frame.png
ffmpeg version 4.4.5-0ubuntu1~22.04.sav0 Copyright (c) 2000-2024 the FFmpeg developers
  built with gcc 11 (Ubuntu 11.4.0-1ubuntu1~22.04)
  configuration: --prefix=/usr --extra-version='0ubuntu1~22.04.sav0' --toolchain=hardened --libdir=/usr/lib/x86_64-linux-gnu --incdir=/usr/include/x86_64-linux-gnu --arch=amd64 --enable-gpl --disable-stripping --enable-gnutls --enable-ladspa --enable-libaom --enable-libass --enable-libbluray --enable-libbs2b --enable-libcaca --enable-libcdio --enable-libcodec2 --enable-libflite --enable-libfontconfig --enable-libfreetype --enable-libfribidi --enable-libgme --enable-libgsm --enable-libjack --enable-libmp3lame --enable-libmysofa --enable-libopenjpeg --enable-libopenmpt --enable-libopus --enable-libpulse --enable-librabbitmq --enable-librubberband --enable-libshine --enable-libsnappy --enable-libsoxr --enable-libspeex --enable-libsrt --enable-libssh --enable-libtheora --enable-libtwolame --enable-libvidstab --enable-libvorbis --enable-libvpx --enable-libwebp --enable-libx265 --enable-libxml2 --enable-libxvid --enable-libzimg --enable-libzmq --enable-libzvbi --enable-lv2 --enable-omx --enable-openal --enable-opencl --enable-opengl --enable-sdl2 --enable-pocketsphinx --enable-librsvg --enable-libdc1394 --enable-libdrm --enable-libiec61883 --enable-chromaprint --enable-frei0r --enable-libx264 --enable-shared
  libavutil      56. 70.100 / 56. 70.100
  libavcodec     58.134.100 / 58.134.100
  libavformat    58. 76.100 / 58. 76.100
  libavdevice    58. 13.100 / 58. 13.100
  libavfilter     7.110.100 /  7.110.100
  libswscale      5.  9.100 /  5.  9.100
  libswresample   3.  9.100 /  3.  9.100
  libpostproc    55.  9.100 / 55.  9.100
[rawvideo @ 0x65301995c080] Estimating duration from bitrate, this may be inaccurate
Input #0, rawvideo, from 'frame.raw':
  Duration: 00:00:00.04, start: 0.000000, bitrate: 1244160 kb/s
  Stream #0:0: Video: rawvideo (RGB[24] / 0x18424752), rgb24, 1920x1080, 1244160 kb/s, 25 tbr, 25 tbn, 25 tbc
Stream mapping:
  Stream #0:0 -&amp;gt; #0:0 (rawvideo (native) -&amp;gt; png (native))
Press [q] to stop, [?] for help
Output #0, image2, to 'frame.png':
  Metadata:
    encoder         : Lavf58.76.100
  Stream #0:0: Video: png, rgb24(progressive), 1920x1080, q=2-31, 200 kb/s, 25 fps, 25 tbn
    Metadata:
      encoder         : Lavc58.134.100 png
frame=    1 fps=0.0 q=-0.0 Lsize=N/A time=00:00:00.04 bitrate=N/A speed=1.05x    
video:10kB audio:0kB subtitle:0kB other streams:0kB global headers:0kB muxing overhead: unknown&lt;/LI-CODE&gt;</description>
      <pubDate>Sun, 02 Mar 2025 10:09:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8mp-clock-configuration-for-MIPI-CSI2/m-p/2054172#M234622</guid>
      <dc:creator>rajtend</dc:creator>
      <dc:date>2025-03-02T10:09:22Z</dc:date>
    </item>
    <item>
      <title>Re: imx8mp clock configuration for MIPI CSI2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-clock-configuration-for-MIPI-CSI2/m-p/2055795#M234715</link>
      <description>&lt;P&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;Unfortunately we do not have this kind of connection available on our EVK, so we may not have examples or references on how to do this.&lt;BR /&gt;&lt;BR /&gt;Also, note that the LVDS does not have connection to the MIPI-CSI2, please refer to the Reference manual&amp;nbsp;Figure 13-1. Display, Imaging, Camera I/F Diagram.&lt;BR /&gt;&lt;BR /&gt;For this I would suggest to reach out either phytec or your module/camera vendor for the correct device tree bindings needed for your implementation.&lt;BR /&gt;&lt;BR /&gt;Best regards/Saludos,&lt;BR /&gt;Aldo.&lt;/P&gt;</description>
      <pubDate>Tue, 04 Mar 2025 22:56:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8mp-clock-configuration-for-MIPI-CSI2/m-p/2055795#M234715</guid>
      <dc:creator>AldoG</dc:creator>
      <dc:date>2025-03-04T22:56:48Z</dc:date>
    </item>
  </channel>
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