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    <title>topic Clarification on LPSPI Usage in MIMX9352CVVXM Processor in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Clarification-on-LPSPI-Usage-in-MIMX9352CVVXM-Processor/m-p/2054116#M234612</link>
    <description>&lt;P&gt;Dear Experts,&lt;/P&gt;&lt;P&gt;Please clarify the following doubts:&lt;/P&gt;&lt;P&gt;1. &lt;EM&gt;What is the maximum number of LPSPI instances that can be used simultaneously on the MIMX9352CVVXM processor?&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;2. &lt;EM&gt;We attempted to assign all available LPSPI instances (8 in total), but LPSPI4 and LPSPI5 signals appear to have the same functionality, preventing us from using all 8 LPSPI instances at the same time. How can we enable all LPSPI instances using the Config Tool?&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;3.&lt;EM&gt; Please provide reference .dts file entries for enabling all LPSPI signals.&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Best regards,&lt;BR /&gt;Ronad&lt;/P&gt;</description>
    <pubDate>Sat, 01 Mar 2025 10:08:45 GMT</pubDate>
    <dc:creator>Embedded-world</dc:creator>
    <dc:date>2025-03-01T10:08:45Z</dc:date>
    <item>
      <title>Clarification on LPSPI Usage in MIMX9352CVVXM Processor</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Clarification-on-LPSPI-Usage-in-MIMX9352CVVXM-Processor/m-p/2054116#M234612</link>
      <description>&lt;P&gt;Dear Experts,&lt;/P&gt;&lt;P&gt;Please clarify the following doubts:&lt;/P&gt;&lt;P&gt;1. &lt;EM&gt;What is the maximum number of LPSPI instances that can be used simultaneously on the MIMX9352CVVXM processor?&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;2. &lt;EM&gt;We attempted to assign all available LPSPI instances (8 in total), but LPSPI4 and LPSPI5 signals appear to have the same functionality, preventing us from using all 8 LPSPI instances at the same time. How can we enable all LPSPI instances using the Config Tool?&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;3.&lt;EM&gt; Please provide reference .dts file entries for enabling all LPSPI signals.&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Best regards,&lt;BR /&gt;Ronad&lt;/P&gt;</description>
      <pubDate>Sat, 01 Mar 2025 10:08:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Clarification-on-LPSPI-Usage-in-MIMX9352CVVXM-Processor/m-p/2054116#M234612</guid>
      <dc:creator>Embedded-world</dc:creator>
      <dc:date>2025-03-01T10:08:45Z</dc:date>
    </item>
    <item>
      <title>Re: Clarification on LPSPI Usage in MIMX9352CVVXM Processor</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Clarification-on-LPSPI-Usage-in-MIMX9352CVVXM-Processor/m-p/2054814#M234664</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/229613"&gt;@Embedded-world&lt;/a&gt;!&lt;/P&gt;
&lt;P&gt;The iMX93 has the power to manage the 8 LPSPI at the same time, unfortunately the LPSPI4 and LPSPI5 share the same pins.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;To solve the problem I can propose the next solutions:&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;1) Use GPIOS as a chip select to control 2 devices using one SPI BUS.&lt;/P&gt;
&lt;P&gt;2) You can use the &lt;SPAN class="sp-hero-others-codeid"&gt;SC18IS606 to control a new SPI device (The SC18IS606 is a i2C to SPI converter)&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN class="sp-hero-others-codeid"&gt;What board are you using?&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;I can help you configuring the dts file directly in your actual dts, please share the file.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best Regards!&lt;/P&gt;
&lt;P&gt;Chavira&lt;/P&gt;</description>
      <pubDate>Mon, 03 Mar 2025 15:27:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Clarification-on-LPSPI-Usage-in-MIMX9352CVVXM-Processor/m-p/2054814#M234664</guid>
      <dc:creator>Chavira</dc:creator>
      <dc:date>2025-03-03T15:27:48Z</dc:date>
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