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    <title>topic imx8mp ethernet mdio clock in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-ethernet-mdio-clock/m-p/2052923#M234541</link>
    <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;We have our own design based on imx8mp and kernel 6.6.23 from NXP.&lt;BR /&gt;We also have the ethernet interface, and this is the device tree configuration:&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;amp;fec {&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;pinctrl-names = &lt;/SPAN&gt;&lt;SPAN&gt;"default"&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;pinctrl-0 = &amp;lt;&amp;amp;pinctrl_fec&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;phy-mode = &lt;/SPAN&gt;&lt;SPAN&gt;"rmii"&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;phy-handle = &amp;lt;&amp;amp;ethphy0&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;phy-supply = &amp;lt;&amp;amp;reg_on_veth&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;status = &lt;/SPAN&gt;&lt;SPAN&gt;"okay"&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;mdio {&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#address-cells = &amp;lt;1&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#size-cells = &amp;lt;0&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;ethphy0: ethernet-phy&lt;/SPAN&gt;&lt;SPAN&gt;@0&lt;/SPAN&gt;&lt;SPAN&gt; {&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;compatible = &lt;/SPAN&gt;&lt;SPAN&gt;"ethernet-phy-ieee802.3-c22"&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;reg = &amp;lt;0&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;nxp,rmii-refclk-in;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;smsc,disable-energy-detect;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;};&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;};&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;};&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;pinctrl_fec: fecgrp {&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;fsl,pins = &amp;lt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x0000001f&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x00000106&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x00000106&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x00000091&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x00000091&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x0000001f&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x0000001f&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x0000001f&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x00000106&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;MX8MP_IOMUXC_SAI1_TXD7__ENET1_TX_ER 0x00000106&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x00000091&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;};&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;P&gt;We have a problem with the "ifconfig eth0 down" command. Most of the time the signal ENET1_MDC (AH9) stays high and sometimes low.&lt;/P&gt;&lt;P&gt;We need to make sure that this signal goes low. When this signal is high and supply to PHY is removed, some milliamps are driven through this pin.&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;Angel&lt;/P&gt;</description>
    <pubDate>Thu, 27 Feb 2025 10:44:50 GMT</pubDate>
    <dc:creator>AngelF</dc:creator>
    <dc:date>2025-02-27T10:44:50Z</dc:date>
    <item>
      <title>imx8mp ethernet mdio clock</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-ethernet-mdio-clock/m-p/2052923#M234541</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;We have our own design based on imx8mp and kernel 6.6.23 from NXP.&lt;BR /&gt;We also have the ethernet interface, and this is the device tree configuration:&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;amp;fec {&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;pinctrl-names = &lt;/SPAN&gt;&lt;SPAN&gt;"default"&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;pinctrl-0 = &amp;lt;&amp;amp;pinctrl_fec&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;phy-mode = &lt;/SPAN&gt;&lt;SPAN&gt;"rmii"&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;phy-handle = &amp;lt;&amp;amp;ethphy0&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;phy-supply = &amp;lt;&amp;amp;reg_on_veth&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;status = &lt;/SPAN&gt;&lt;SPAN&gt;"okay"&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;mdio {&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#address-cells = &amp;lt;1&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#size-cells = &amp;lt;0&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;ethphy0: ethernet-phy&lt;/SPAN&gt;&lt;SPAN&gt;@0&lt;/SPAN&gt;&lt;SPAN&gt; {&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;compatible = &lt;/SPAN&gt;&lt;SPAN&gt;"ethernet-phy-ieee802.3-c22"&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;reg = &amp;lt;0&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;nxp,rmii-refclk-in;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;smsc,disable-energy-detect;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;};&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;};&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;};&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;pinctrl_fec: fecgrp {&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;fsl,pins = &amp;lt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x0000001f&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x00000106&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x00000106&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x00000091&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x00000091&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x0000001f&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x0000001f&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x0000001f&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x00000106&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;MX8MP_IOMUXC_SAI1_TXD7__ENET1_TX_ER 0x00000106&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x00000091&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;};&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;P&gt;We have a problem with the "ifconfig eth0 down" command. Most of the time the signal ENET1_MDC (AH9) stays high and sometimes low.&lt;/P&gt;&lt;P&gt;We need to make sure that this signal goes low. When this signal is high and supply to PHY is removed, some milliamps are driven through this pin.&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;Angel&lt;/P&gt;</description>
      <pubDate>Thu, 27 Feb 2025 10:44:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8mp-ethernet-mdio-clock/m-p/2052923#M234541</guid>
      <dc:creator>AngelF</dc:creator>
      <dc:date>2025-02-27T10:44:50Z</dc:date>
    </item>
    <item>
      <title>Re: imx8mp ethernet mdio clock</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-ethernet-mdio-clock/m-p/2053092#M234555</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Thank you for your interest in NXP Semiconductor products,&lt;/P&gt;
&lt;P&gt;You can try to add another pinctrl handle for sleep and when the interface is down, write to the MDC pin as GPIO through filesystem.&lt;/P&gt;
&lt;P&gt;Regards&lt;/P&gt;</description>
      <pubDate>Thu, 27 Feb 2025 16:01:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8mp-ethernet-mdio-clock/m-p/2053092#M234555</guid>
      <dc:creator>JosephAtNXP</dc:creator>
      <dc:date>2025-02-27T16:01:07Z</dc:date>
    </item>
    <item>
      <title>Re: imx8mp ethernet mdio clock</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-ethernet-mdio-clock/m-p/2053538#M234578</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;Thank you for your answer.&lt;/P&gt;&lt;P&gt;I have added&amp;nbsp;&lt;SPAN&gt;pinctrl handle for sleep and it seems to drive pin to low, both when I set the interface down and when I enter standby mode.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Best regards and thank you&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 28 Feb 2025 06:52:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8mp-ethernet-mdio-clock/m-p/2053538#M234578</guid>
      <dc:creator>AngelF</dc:creator>
      <dc:date>2025-02-28T06:52:02Z</dc:date>
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