<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: GPIO input detection via M7-core in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/GPIO-input-detection-via-M7-core/m-p/2043441#M233971</link>
    <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/203368"&gt;@Manuel_Salas&lt;/a&gt;&amp;nbsp;,&lt;BR /&gt;Any update on above issue?&amp;nbsp;&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Pratham&lt;/P&gt;</description>
    <pubDate>Thu, 13 Feb 2025 13:23:03 GMT</pubDate>
    <dc:creator>pratham_malaviya</dc:creator>
    <dc:date>2025-02-13T13:23:03Z</dc:date>
    <item>
      <title>GPIO input detection via M7-core</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/GPIO-input-detection-via-M7-core/m-p/2038686#M233650</link>
      <description>&lt;P&gt;Hi there,&amp;nbsp;&lt;/P&gt;&lt;P&gt;We are implementing a system in which we are detecting up to 1 MHz of PWM signal on the input GPIO pin.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Now the issue we are facing is high read latencies.&lt;/P&gt;&lt;P&gt;Here are test cases with the approaches I used:&lt;/P&gt;&lt;P&gt;First, we took a pair of input and output GPIOs.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Approach-1: Polling&lt;/STRONG&gt;&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;Keep reading the state of the input GPIO and copy it to the output GPIO.&lt;/LI&gt;&lt;LI&gt;Tested Frequencies: 100 kHz, 500 kHz, and 1 MHz.&amp;nbsp;&lt;/LI&gt;&lt;LI&gt;Fast slew rate of output GPIO.&lt;/LI&gt;&lt;LI&gt;Tried implementing bare metal instead of wrapper functions.&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;STRONG&gt;Conclusion:&lt;/STRONG&gt;&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;Till 100 kHz it works fine, but on higher frequencies there are hard delays of around ~1.5. us.&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;STRONG&gt;Approach-2: Using Interrupt&lt;/STRONG&gt;&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;Configure the input pin as an IRQ source, and when the rising edge is detected, toggle the output GPIO from ISR.&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;STRONG&gt;Conclusion:&lt;/STRONG&gt;&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;Same as the polling approach when the PWM frequency was at 500 kHz. The interrupts were missed.&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;So, my queries are as below:&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;What are the causes of these hard delays?&lt;/LI&gt;&lt;LI&gt;Is it theoretically possible to do what we are trying?&lt;/LI&gt;&lt;LI&gt;Any other possible approach you can suggest&amp;gt;&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;Thanks and regards,&lt;/P&gt;&lt;P&gt;Pratham.&lt;/P&gt;</description>
      <pubDate>Wed, 05 Feb 2025 15:42:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/GPIO-input-detection-via-M7-core/m-p/2038686#M233650</guid>
      <dc:creator>pratham_malaviya</dc:creator>
      <dc:date>2025-02-05T15:42:04Z</dc:date>
    </item>
    <item>
      <title>Re: GPIO input detection via M7-core</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/GPIO-input-detection-via-M7-core/m-p/2038948#M233662</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/235882"&gt;@pratham_malaviya&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I hope you are doing very well.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Theoretically, It should be possible, but&amp;nbsp;accessing GPIOs through the general-purpose I/O registers (even when using bare metal) has inherent latencies due to memory access overhead.&lt;/P&gt;
&lt;P&gt;You can try to use RTOS and use the&amp;nbsp;taskENTER_CRITICAL() function and measure if there is an improvement.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I hope this can helps to you.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Salas.&lt;/P&gt;</description>
      <pubDate>Thu, 06 Feb 2025 02:33:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/GPIO-input-detection-via-M7-core/m-p/2038948#M233662</guid>
      <dc:creator>Manuel_Salas</dc:creator>
      <dc:date>2025-02-06T02:33:22Z</dc:date>
    </item>
    <item>
      <title>Re: GPIO input detection via M7-core</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/GPIO-input-detection-via-M7-core/m-p/2039307#M233693</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/203368"&gt;@Manuel_Salas&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;&lt;P&gt;Thank you for your support!&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;As per your suggestion, I implemented it using RTOS, but some hard delays still remain.&lt;/P&gt;&lt;P&gt;I am attaching a code snippet and a logic analyzer capture for your reference.&lt;/P&gt;&lt;P&gt;&lt;EM&gt;Channel-1: Output GPIO&amp;nbsp;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Channel-2: PWM signal fed to input GPIO.&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;I am still confused about these hard delays. The clock root for the GPIO is around 133 MHz, yet register access still takes a significant amount of time.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;LI-CODE lang="c"&gt;static void hello_task(void *pvParameters)
{   
    for (;;)
    {
    //    PRINTF("Hello world.\r\n");
        taskENTER_CRITICAL();
        state = GPIO_PinRead(INPUT_GPIO,INPUT_GPIO_PIN);
        GPIO_PinWrite(EXAMPLE_LED_GPIO,EXAMPLE_LED_GPIO_PIN,state);
        taskEXIT_CRITICAL();
       // vTaskSuspend(NULL);
    }  
}   &lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 06 Feb 2025 11:54:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/GPIO-input-detection-via-M7-core/m-p/2039307#M233693</guid>
      <dc:creator>pratham_malaviya</dc:creator>
      <dc:date>2025-02-06T11:54:55Z</dc:date>
    </item>
    <item>
      <title>Re: GPIO input detection via M7-core</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/GPIO-input-detection-via-M7-core/m-p/2043441#M233971</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/203368"&gt;@Manuel_Salas&lt;/a&gt;&amp;nbsp;,&lt;BR /&gt;Any update on above issue?&amp;nbsp;&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Pratham&lt;/P&gt;</description>
      <pubDate>Thu, 13 Feb 2025 13:23:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/GPIO-input-detection-via-M7-core/m-p/2043441#M233971</guid>
      <dc:creator>pratham_malaviya</dc:creator>
      <dc:date>2025-02-13T13:23:03Z</dc:date>
    </item>
  </channel>
</rss>

