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    <title>i.MX Processorsのトピックinformation needed</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/information-needed/m-p/2040896#M233813</link>
    <description>&lt;P&gt;i am using imx8mplus custom board . i want to blink the leds which are connected to my board&lt;BR /&gt;gpio3 port , pin19,20,21,25&lt;BR /&gt;the below changes i made in my dts file , leds are blinking fine . i want to know what is 0x400000.&lt;BR /&gt;which register they are configuring and how it behaves gpio . please let me know .&lt;BR /&gt;&lt;BR /&gt;&amp;amp;gpio3 {&lt;BR /&gt;pinctrl-names = "default";&lt;BR /&gt;pinctrl-0 = &amp;lt;&amp;amp;pinctrl_gpio3&amp;gt;;&lt;BR /&gt;&lt;BR /&gt;status = "okay";&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Then, inside of the &amp;amp;iomuxc:&lt;/P&gt;&lt;P&gt;pinctrl_gpio3: gpio3grp {&lt;BR /&gt;fsl,pins = &amp;lt;&lt;BR /&gt;MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x40000&lt;BR /&gt;MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x40000&lt;BR /&gt;MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x40000&lt;BR /&gt;MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x40000&lt;BR /&gt;&amp;gt;;&lt;BR /&gt;};&lt;/P&gt;</description>
    <pubDate>Mon, 10 Feb 2025 12:21:03 GMT</pubDate>
    <dc:creator>srinivas_123</dc:creator>
    <dc:date>2025-02-10T12:21:03Z</dc:date>
    <item>
      <title>information needed</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/information-needed/m-p/2040896#M233813</link>
      <description>&lt;P&gt;i am using imx8mplus custom board . i want to blink the leds which are connected to my board&lt;BR /&gt;gpio3 port , pin19,20,21,25&lt;BR /&gt;the below changes i made in my dts file , leds are blinking fine . i want to know what is 0x400000.&lt;BR /&gt;which register they are configuring and how it behaves gpio . please let me know .&lt;BR /&gt;&lt;BR /&gt;&amp;amp;gpio3 {&lt;BR /&gt;pinctrl-names = "default";&lt;BR /&gt;pinctrl-0 = &amp;lt;&amp;amp;pinctrl_gpio3&amp;gt;;&lt;BR /&gt;&lt;BR /&gt;status = "okay";&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Then, inside of the &amp;amp;iomuxc:&lt;/P&gt;&lt;P&gt;pinctrl_gpio3: gpio3grp {&lt;BR /&gt;fsl,pins = &amp;lt;&lt;BR /&gt;MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x40000&lt;BR /&gt;MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x40000&lt;BR /&gt;MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x40000&lt;BR /&gt;MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x40000&lt;BR /&gt;&amp;gt;;&lt;BR /&gt;};&lt;/P&gt;</description>
      <pubDate>Mon, 10 Feb 2025 12:21:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/information-needed/m-p/2040896#M233813</guid>
      <dc:creator>srinivas_123</dc:creator>
      <dc:date>2025-02-10T12:21:03Z</dc:date>
    </item>
    <item>
      <title>Re: information needed</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/information-needed/m-p/2040975#M233820</link>
      <description>&lt;P&gt;HI &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/231093"&gt;@srinivas_123&lt;/a&gt;!&lt;/P&gt;
&lt;P&gt;Thank you for contacting NXP Support!&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The next line configures 2 Registers:&lt;/P&gt;
&lt;LI-CODE lang="markup"&gt;MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x40000&lt;/LI-CODE&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;1.&amp;nbsp;SW_MUX_CTL_PAD_SAI5_RXFS&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;2. SW_PAD_CTL_PAD_SAI5_RXFS&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The first element of the configuration is :&lt;/P&gt;
&lt;LI-CODE lang="markup"&gt;MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19&lt;/LI-CODE&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;this part configures the &lt;STRONG&gt;SW_MUX_CTL_PAD_SAI5_RXFS&lt;/STRONG&gt; register and is divided in two parts:&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;1. Pad name:&lt;/STRONG&gt;&amp;nbsp; MX8MP_IOMUXC_SAI5_RXFS&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;2. Function name:&lt;/STRONG&gt; __GPIO3_IO19&lt;/P&gt;
&lt;P&gt;You can consult each function of each pin in the Reference Manual of the device.&lt;/P&gt;
&lt;P&gt;This functions are declared on the pinfunc.h of each device in this case is &lt;A href="https://github.com/nxp-imx/linux-imx/blob/lf-6.6.y/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h" target="_self"&gt;imx8mp-pinfunc.h&lt;/A&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The second element of the configuration is :&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;LI-CODE lang="markup"&gt;0x40000&lt;/LI-CODE&gt;
&lt;P&gt;This value is directly the value that we write in &lt;STRONG&gt;SW_PAD_CTL_PAD_SAI5_RXFS&lt;/STRONG&gt;.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best Regards!&lt;/P&gt;
&lt;P&gt;Chavira&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 10 Feb 2025 14:44:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/information-needed/m-p/2040975#M233820</guid>
      <dc:creator>Chavira</dc:creator>
      <dc:date>2025-02-10T14:44:07Z</dc:date>
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