topic Re: Enable UART5 in 3.0.35 kernel in i.MX Processors

Enable UART5 in 3.0.35 kernel

frankmiller — Thu, 04 Apr 2013 21:07:09 GMT

How do I enable uart5 in the 3.0.35 linux kernel build for an i.MX6Q SabreSD based design?

Thanks,

Re: Enable UART5 in 3.0.35 kernel

4guin4g4 — Mon, 08 Apr 2013 17:34:40 GMT

You need to make the following modificationsto the IO Muxing and UART init:

static iomux_v3_cfg_t albany_mx6q_pads[] = {

...

MX6Q_PAD_KEY_COL1__UART5_TXD,

MX6Q_PAD_KEY_ROW1__UART5_RXD,

MX6Q_PAD_KEY_COL4__UART5_RTS,

MX6Q_PAD_KEY_ROW4__UART5_CTS,

...

}

static const struct imxuart_platform_data mx6_arm2_uart4_data __initconst = {

.flags = IMXUART_HAVE_RTSCTS | IMXUART_SDMA,

.dma_req_rx = MX6Q_DMA_REQ_UART5_RX,

.dma_req_tx = MX6Q_DMA_REQ_UART5_TX,

};

static inline void mx6_arm2_init_uart(void)

{

imx6q_add_imx_uart(2, NULL); // UART 3

imx6q_add_imx_uart(4, &mx6_arm2_uart4_data); // UART 5

}

After that you may want to take a look at :

https://community.freescale.com/message/300061#300061

Re: Enable UART5 in 3.0.35 kernel

frankmiller — Mon, 08 Apr 2013 20:52:01 GMT

Greetings and thanks for the reply!

I got the iomux changes but I'm using a SabreSD based reference design so where would I make the UART init changes that refer to in that build?

Thanks,

Re: Enable UART5 in 3.0.35 kernel

frankmiller — Tue, 09 Apr 2013 16:13:55 GMT

Hi Carlos,

Thanks for the reply. As I mentioned, I made the IOMux pin changes you suggested and I've also done the following changes in board-mx6q_sabresd.c:

// <added>

static const struct imxuart_platform_data

mx6_sabresd_uart4_data __initconst = {

.flags = IMXUART_HAVE_RTSCTS | IMXUART_SDMA,

.dma_req_rx = MX6Q_DMA_REQ_UART5_RX,

.dma_req_tx = MX6Q_DMA_REQ_UART5_TX,

};

// </added>

static inline void mx6q_sabresd_init_uart(void)

{

imx6q_add_imx_uart(0, NULL);

// imx6q_add_imx_uart(2, NULL);

imx6q_add_imx_uart(4, &mx6_sabresd_uart4_data);

// imx6q_add_imx_uart(4, NULL);

// imx6q_add_imx_uart(0, NULL);

}

This is the output I get when I try to boot this. For some reason it doesnt appear to be applying these parameters to UART5. The kernel boot hangs at this point as well. Any thoughts?

imx-sdma imx-sdma: loaded firmware 1.1

imx-sdma imx-sdma: initialized

Serial: IMX driver

imx-uart.0: ttymxc0 at MMIO 0x2020000 (irq = 58) is a IMX

console [ttymxc0] enabled, bootconsole disabled

imx-uart.1: ttymxc1 at MMIO 0x2184200 (irq = 2) is a IMX

Re: Enable UART5 in 3.0.35 kernel

waterzhou — Fri, 19 Apr 2013 02:00:15 GMT

There is hardware conflicts between UART5 and pcie in i.MX6Q SabreSD. So if you want to enable uart5 you can refer to the following hardware rework.Then for software patch, you can get our newest code in our android branch. We have enable it in kernel to support BT in android.

https://community.freescale.com/docs/DOC-94235

I think you also need the below changes except IO Muxing and UART init in board-mx6q_sabresd.c,You can refer to what we changed in our new codes:

diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c

index 0a8c880..8354428 100644

--- a/arch/arm/mach-mx6/clock.c

+++ b/arch/arm/mach-mx6/clock.c

@@ -1,6 +1,6 @@

@@ -5258,6 +5258,7 @@ static struct clk_lookup lookups[] = {

_REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[0]),

_REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[0]),

_REGISTER_CLOCK("imx-uart.3", NULL, uart_clk[0]),

+ _REGISTER_CLOCK("imx-uart.4", NULL, uart_clk[0]),

_REGISTER_CLOCK(NULL, "hsi_tx", hsi_tx_clk[0]),

_REGISTER_CLOCK(NULL, "caam_clk", caam_clk[0]),

_REGISTER_CLOCK(NULL, "asrc_clk", asrc_clk[0]),

diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c

index 7f70dc9..e76b026 100644

--- a/arch/arm/plat-mxc/devices/platform-imx-uart.c

+++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c

@@ -134,6 +134,7 @@ const struct imx_imx_uart_1irq_data imx6q_imx_uart_data[] __initconst = {

imx6q_imx_uart_data_entry(1, 2),

imx6q_imx_uart_data_entry(2, 3),

imx6q_imx_uart_data_entry(3, 4),

+ imx6q_imx_uart_data_entry(4, 5),

};

#endif /* ifdef CONFIG_SOC_IMX6Q */

diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h

index cdff320..c1acc24 100644

--- a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h

+++ b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h

@@ -1,5 +1,5 @@

@@ -2249,7 +2249,7 @@

#define _MX6Q_PAD_KEY_ROW4__KPP_ROW_4 \

IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0)

#define _MX6Q_PAD_KEY_ROW4__UART5_CTS \

- IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0)

+ IOMUX_PAD(0x05EC, 0x021C, 4, 0x0000, 0, 0)

#define _MX6Q_PAD_KEY_ROW4__GPIO_4_15 \

IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0)

#define _MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 \

diff --git a/arch/arm/plat-mxc/include/mach/mx6.h b/arch/arm/plat-mxc/include/mach/mx6.h

index bb22de0..ba38b8a 100644

--- a/arch/arm/plat-mxc/include/mach/mx6.h

+++ b/arch/arm/plat-mxc/include/mach/mx6.h

@@ -283,6 +283,8 @@

#define MX6Q_UART2_BASE_ADDR UART2_BASE_ADDR

#define MX6Q_UART3_BASE_ADDR UART3_BASE_ADDR

#define MX6Q_UART4_BASE_ADDR UART4_BASE_ADDR

+#define MX6Q_UART5_BASE_ADDR UART5_BASE_ADDR

#define MX6Q_FEC_BASE_ADDR ENET_BASE_ADDR

#define MX6DL_FEC_BASE_ADDR ENET_BASE_ADDR

#define MX6Q_MIPI_DSI_BASE_ADDR MIPI_DSI_BASE_ADDR

@@ -486,6 +488,7 @@

#define MX6Q_INT_UART2 MXC_INT_UART2_ANDED

#define MX6Q_INT_UART3 MXC_INT_UART3_ANDED

#define MX6Q_INT_UART4 MXC_INT_UART4_ANDED

+#define MX6Q_INT_UART5 MXC_INT_UART5_ANDED

#define MX6SL_INT_UART1 MXC_INT_UART1_ANDED

#define MX6SL_INT_UART2 MXC_INT_UART2_ANDED

#define MX6SL_INT_UART3 MXC_INT_UART3_ANDED

Re: Enable UART5 in 3.0.35 kernel

frankmiller — Fri, 19 Apr 2013 05:54:43 GMT

I was finally able to get this to work. See my reply in the second thread that I somehow got started on this entitled UART5 getty under Ubuntu Linux I give the source code diffs from the 3.0.35 kernel there.