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    <title>i.MX ProcessorsのトピックRe: IMX8M Plus ECSPI slave mode DMA restriction</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX8M-Plus-ECSPI-slave-mode-DMA-restriction/m-p/2040247#M233756</link>
    <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/246319"&gt;@atessadri&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;We have not done such testing, but i think you are right,&amp;nbsp;If you can fully control the transfer on the SPI master side and ensure that all data blocks are 4-byte aligned, then using DMA for ECSPI slave data reception is theoretically feasible, but the ECSPI driver may need to be appropriately modified to support DMA transfer in slave mode.&lt;/P&gt;
&lt;P&gt;B.R&lt;/P&gt;</description>
    <pubDate>Sat, 08 Feb 2025 01:10:49 GMT</pubDate>
    <dc:creator>pengyong_zhang</dc:creator>
    <dc:date>2025-02-08T01:10:49Z</dc:date>
    <item>
      <title>IMX8M Plus ECSPI slave mode DMA restriction</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8M-Plus-ECSPI-slave-mode-DMA-restriction/m-p/2039265#M233689</link>
      <description>&lt;P&gt;According to NXP document attached&amp;nbsp;AN13633 it seams not possible to use DMA when ECSPI controller is used in slave mode.&lt;/P&gt;&lt;BLOCKQUOTE&gt;&lt;P&gt;&lt;FONT size="2"&gt;This limitation has the following effects on driver:&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;1. In slave mode, DMA can’t be used. Instead, only PIO mode can be used. It is based on the following&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;considerations:&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;a. To use DMA mode, the burst size must be 4 byte aligned.&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;b. The ECSPI driver must support unaligned transfer size.&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;2. The burst size must be set to transfer size in PIO mode. But maximum burst size is 2^12 = 512 bytes. So&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;ECSPI driver can transfer maximum 512 bytes in a PIO transfer.&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;&lt;STRONG&gt;Note&lt;/STRONG&gt;: From testing, &lt;U&gt;it seems no such transfer length restriction must be added in DMA mode&lt;/U&gt;. So only PIO&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;mode has this restriction.&lt;/FONT&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;Anyway in the footer note it says there is no such transfer restriction, so I am wondering if DMA can be used as well with a data transfer 4 bytes aligned.&lt;/P&gt;&lt;P&gt;We have complete control on the slave master sending packets, so we can be compliant with the restriction to use a 4 bytes aligned transfer.&lt;/P&gt;&lt;P&gt;Will it be enough to have DMA transfer with ECSPI in slave mode ?&lt;/P&gt;&lt;P&gt;Our idea is to trigger a SMART DMA script for each SPI received packet so that a dedicated memory buffer will be filled with packed content according to an index added to the packet header to calculate the buffer offset where to copy packet data.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp;Andrea&lt;/P&gt;</description>
      <pubDate>Thu, 06 Feb 2025 10:25:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8M-Plus-ECSPI-slave-mode-DMA-restriction/m-p/2039265#M233689</guid>
      <dc:creator>atessadri</dc:creator>
      <dc:date>2025-02-06T10:25:40Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8M Plus ECSPI slave mode DMA restriction</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8M-Plus-ECSPI-slave-mode-DMA-restriction/m-p/2040247#M233756</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/246319"&gt;@atessadri&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;We have not done such testing, but i think you are right,&amp;nbsp;If you can fully control the transfer on the SPI master side and ensure that all data blocks are 4-byte aligned, then using DMA for ECSPI slave data reception is theoretically feasible, but the ECSPI driver may need to be appropriately modified to support DMA transfer in slave mode.&lt;/P&gt;
&lt;P&gt;B.R&lt;/P&gt;</description>
      <pubDate>Sat, 08 Feb 2025 01:10:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8M-Plus-ECSPI-slave-mode-DMA-restriction/m-p/2040247#M233756</guid>
      <dc:creator>pengyong_zhang</dc:creator>
      <dc:date>2025-02-08T01:10:49Z</dc:date>
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