<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックRe: Understanding GPIO Number Calculation for GPIO2_IO00 on IMX9352 Board</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Understanding-GPIO-Number-Calculation-for-GPIO2-IO00-on-IMX9352/m-p/2040095#M233751</link>
    <description>dear,&lt;BR /&gt;take a look to the example:&lt;BR /&gt;if you want to export the GPIO1_IO_25;&lt;BR /&gt;&lt;BR /&gt;# GPIO1_IO_25 means BANK=1 and ID=25&lt;BR /&gt;# GPIO_NUMBER = ((1 - 1) * 32 ) + 25 = 25&lt;BR /&gt;&lt;BR /&gt;for the complete documentation use the next link&lt;BR /&gt;&lt;A href="https://www.udoo.org/docs/Hardware_Accessories/GPIO_Pinout.html" target="_blank"&gt;https://www.udoo.org/docs/Hardware_Accessories/GPIO_Pinout.html&lt;/A&gt; &lt;BR /&gt;&lt;BR /&gt;for a kernel GPIO info&lt;BR /&gt;&lt;A href="https://www.kernel.org/doc/Documentation/gpio/sysfs.rst" target="_blank"&gt;https://www.kernel.org/doc/Documentation/gpio/sysfs.rst&lt;/A&gt;&lt;BR /&gt;&lt;BR /&gt;regards &lt;BR /&gt;LFGP</description>
    <pubDate>Fri, 07 Feb 2025 16:24:35 GMT</pubDate>
    <dc:creator>LFGP</dc:creator>
    <dc:date>2025-02-07T16:24:35Z</dc:date>
    <item>
      <title>Understanding GPIO Number Calculation for GPIO2_IO00 on IMX9352 Board</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Understanding-GPIO-Number-Calculation-for-GPIO2-IO00-on-IMX9352/m-p/2034920#M233412</link>
      <description>&lt;P&gt;Dear Experts,&lt;/P&gt;&lt;P&gt;&lt;EM&gt;I'm working on a custom board based on the IMX9352 NPU processor. This board includes an RS485 peripheral, for which we are using GPIO (GPIO2_IO00) to control the enable pin by toggling it between logic high and logic low.&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;To test the RS485 peripheral interface, I need to toggle through echo command the GPIO pin state (high or low). From the community page, I found a way to determine the GPIO number by inspecting the GPIO mappings. The following command displays the GPIO mapping:&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;root@imx93evk:/# cat /sys/kernel/debug/gpio&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;For our board, the output is as follows&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;&lt;STRONG&gt;root@imx93evk:/# cat /sys/kernel/debug/gpio&lt;/STRONG&gt; &lt;/EM&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;root@imx93-11x11-lpddr4x-pf0900-evk:~# cat /sys/kernel/debug/gpio &lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;FONT face="arial,helvetica,sans-serif"&gt;gpiochip0: GPIOs 512-543, parent: platform/43810000.gpio, 43810000.gpio:&lt;/FONT&gt;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;&lt;FONT face="arial,helvetica,sans-serif"&gt;gpiochip1: GPIOs 544-575, parent: platform/43820000.gpio, 43820000.gpio: &lt;/FONT&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;FONT face="arial,helvetica,sans-serif"&gt;gpio-544 ( |cd ) in lo IRQ ACTIVE LOW&lt;/FONT&gt;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;&lt;FONT face="arial,helvetica,sans-serif"&gt;gpiochip2: GPIOs 576-607, parent: platform/43830000.gpio, 43830000.gpio:&lt;/FONT&gt;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;&lt;FONT face="arial,helvetica,sans-serif"&gt;gpiochip3: GPIOs 608-639, parent: platform/47400000.gpio, 47400000.gpio:&lt;/FONT&gt;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;I'm currently using GPIO number &lt;STRONG&gt;512&lt;/STRONG&gt; for &lt;STRONG&gt;GPIO2_IO00,&lt;/STRONG&gt; and it is working fine. but, I want to understand more about how the GPIO numbers are calculated.&lt;/P&gt;&lt;P&gt;Specifically:&lt;/P&gt;&lt;P&gt;1. &lt;STRONG&gt;What is the exact GPIO number for GPIO2_IO00?&lt;/STRONG&gt;&lt;BR /&gt;2. &lt;STRONG&gt;How can I calculate the GPIO number of GPIO2_IO00 using a formula?&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;Thank you for your guidance in advance.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Thanks &amp;amp; Regards,&lt;/P&gt;&lt;P&gt;Ravikumar&lt;/P&gt;</description>
      <pubDate>Tue, 28 Jan 2025 06:33:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Understanding-GPIO-Number-Calculation-for-GPIO2-IO00-on-IMX9352/m-p/2034920#M233412</guid>
      <dc:creator>Embedded-world</dc:creator>
      <dc:date>2025-01-28T06:33:18Z</dc:date>
    </item>
    <item>
      <title>Re: Understanding GPIO Number Calculation for GPIO2_IO00 on IMX9352 Board</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Understanding-GPIO-Number-Calculation-for-GPIO2-IO00-on-IMX9352/m-p/2040095#M233751</link>
      <description>dear,&lt;BR /&gt;take a look to the example:&lt;BR /&gt;if you want to export the GPIO1_IO_25;&lt;BR /&gt;&lt;BR /&gt;# GPIO1_IO_25 means BANK=1 and ID=25&lt;BR /&gt;# GPIO_NUMBER = ((1 - 1) * 32 ) + 25 = 25&lt;BR /&gt;&lt;BR /&gt;for the complete documentation use the next link&lt;BR /&gt;&lt;A href="https://www.udoo.org/docs/Hardware_Accessories/GPIO_Pinout.html" target="_blank"&gt;https://www.udoo.org/docs/Hardware_Accessories/GPIO_Pinout.html&lt;/A&gt; &lt;BR /&gt;&lt;BR /&gt;for a kernel GPIO info&lt;BR /&gt;&lt;A href="https://www.kernel.org/doc/Documentation/gpio/sysfs.rst" target="_blank"&gt;https://www.kernel.org/doc/Documentation/gpio/sysfs.rst&lt;/A&gt;&lt;BR /&gt;&lt;BR /&gt;regards &lt;BR /&gt;LFGP</description>
      <pubDate>Fri, 07 Feb 2025 16:24:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Understanding-GPIO-Number-Calculation-for-GPIO2-IO00-on-IMX9352/m-p/2040095#M233751</guid>
      <dc:creator>LFGP</dc:creator>
      <dc:date>2025-02-07T16:24:35Z</dc:date>
    </item>
    <item>
      <title>Re: Understanding GPIO Number Calculation for GPIO2_IO00 on IMX9352 Board</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Understanding-GPIO-Number-Calculation-for-GPIO2-IO00-on-IMX9352/m-p/2040322#M233762</link>
      <description>&lt;P&gt;I totally disagree with LFGP's explanation. A Linux driver cannot rely on a chip/chip manual. Here is what LFGP said, GPIO1_IO_25.&lt;/P&gt;&lt;P&gt;# GPIO1_IO_25 ​​means BANK=1 and ID=25&lt;/P&gt;&lt;P&gt;# GPIO_NUMBER = ((1 - 1) * 32 ) + 25 = 25&lt;/P&gt;&lt;P&gt;According to LFGP, GPIO2_IO00 should be 32,&lt;BR /&gt;((2 - 1) * 32 ) + 0 = 32&lt;BR /&gt;But Embedded-world says&lt;BR /&gt;“I'm currently using GPIO number 512 for GPIO2_IO00, and it is working fine. but, I want to understand more about how the GPIO numbers are calculated.”&lt;/P&gt;&lt;P&gt;This is the description of Documentation/gpio/sysfs.rst.&lt;BR /&gt;It is very obvious that the number of gpio in the Linux system depends on base and ngpio.&lt;BR /&gt;This is the log of Embedded-world.&lt;/P&gt;&lt;P&gt;"root@imx93-11x11-lpddr4x-pf0900-evk:~# cat /sys/kernel/debug/gpio&lt;BR /&gt;gpiochip0: GPIOs 512-543, parent: platform/43810000.gpio, 43810000.gpio:"&lt;/P&gt;&lt;P&gt;Because NXP's bsp wrote the order of gpio2 wrong in the device tree, it was displayed as gpiochip0 in Linux. But no matter what, it is calculated according to base + ngpio.&lt;/P&gt;&lt;P&gt;gpiochip0: GPIOs 512-543 32-bit serial numbers are from 512 to 543.&lt;/P&gt;&lt;P&gt;Documentation/gpio/sysfs.rs&lt;BR /&gt;GPIO controllers have paths like /sys/class/gpio/gpiochip42/ (for the&lt;BR /&gt;controller implementing GPIOs starting at #42) and have the following&lt;BR /&gt;read-only attributes:&lt;/P&gt;&lt;P&gt;/sys/class/gpio/gpiochipN/&lt;/P&gt;&lt;P&gt;"base" ...&lt;BR /&gt;same as N, the first GPIO managed by this chip&lt;/P&gt;&lt;P&gt;"label" ...&lt;BR /&gt;provided for diagnostics (not always unique)&lt;/P&gt;&lt;P&gt;"ngpio" ...&lt;BR /&gt;how many GPIOs this manages (N to N + ngpio - 1)&lt;/P&gt;&lt;P&gt;In addition, this article also explains how to calculate the gpio number.&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Accessing-GPIO-From-UserSpace/ta-p/1102710" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Accessing-GPIO-From-UserSpace/ta-p/1102710&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;I can't understand why Embedded-world&amp;nbsp; marked this answer as the correct answer, which caused misunderstanding to subsequent readers.&lt;/P&gt;&lt;P&gt;The gpio order in the device tree is wrong, causing Linux to display gpio2 as gpiochip0: GPIOs 512-543.&lt;/P&gt;&lt;P&gt;gpio2 is the first one in device tree.&lt;/P&gt;&lt;LI-CODE lang="markup"&gt;	gpio2: gpio@43810000 {
			compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
			reg = &amp;lt;0x43810000 0x1000&amp;gt;;
			gpio-controller;
			#gpio-cells = &amp;lt;2&amp;gt;;
			interrupts = &amp;lt;GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH&amp;gt;,
				     &amp;lt;GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH&amp;gt;;
			interrupt-controller;
			#interrupt-cells = &amp;lt;2&amp;gt;;
			clocks = &amp;lt;&amp;amp;clk IMX93_CLK_GPIO2_GATE&amp;gt;,
				 &amp;lt;&amp;amp;clk IMX93_CLK_GPIO2_GATE&amp;gt;;
			clock-names = "gpio", "port";
			gpio-ranges = &amp;lt;&amp;amp;iomuxc 0 4 30&amp;gt;;
		};

		gpio3: gpio@43820000 {
			compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
			reg = &amp;lt;0x43820000 0x1000&amp;gt;;
			gpio-controller;
			#gpio-cells = &amp;lt;2&amp;gt;;
			interrupts = &amp;lt;GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH&amp;gt;,
				     &amp;lt;GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH&amp;gt;;
			interrupt-controller;
			#interrupt-cells = &amp;lt;2&amp;gt;;
			clocks = &amp;lt;&amp;amp;clk IMX93_CLK_GPIO3_GATE&amp;gt;,
				 &amp;lt;&amp;amp;clk IMX93_CLK_GPIO3_GATE&amp;gt;;
			clock-names = "gpio", "port";
			gpio-ranges = &amp;lt;&amp;amp;iomuxc 0 84 8&amp;gt;, &amp;lt;&amp;amp;iomuxc 8 66 18&amp;gt;,
				      &amp;lt;&amp;amp;iomuxc 26 34 2&amp;gt;, &amp;lt;&amp;amp;iomuxc 28 0 4&amp;gt;;
		};

		gpio4: gpio@43830000 {
			compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
			reg = &amp;lt;0x43830000 0x1000&amp;gt;;
			gpio-controller;
			#gpio-cells = &amp;lt;2&amp;gt;;
			interrupts = &amp;lt;GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH&amp;gt;,
				     &amp;lt;GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH&amp;gt;;
			interrupt-controller;
			#interrupt-cells = &amp;lt;2&amp;gt;;
			clocks = &amp;lt;&amp;amp;clk IMX93_CLK_GPIO4_GATE&amp;gt;,
				 &amp;lt;&amp;amp;clk IMX93_CLK_GPIO4_GATE&amp;gt;;
			clock-names = "gpio", "port";
			gpio-ranges = &amp;lt;&amp;amp;iomuxc 0 38 28&amp;gt;, &amp;lt;&amp;amp;iomuxc 28 36 2&amp;gt;;
		};

		gpio1: gpio@47400000 {
			compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
			reg = &amp;lt;0x47400000 0x1000&amp;gt;;
			gpio-controller;
			#gpio-cells = &amp;lt;2&amp;gt;;
			interrupts = &amp;lt;GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH&amp;gt;,
				     &amp;lt;GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH&amp;gt;;
			interrupt-controller;
			#interrupt-cells = &amp;lt;2&amp;gt;;
			clocks = &amp;lt;&amp;amp;clk IMX93_CLK_GPIO1_GATE&amp;gt;,
				 &amp;lt;&amp;amp;clk IMX93_CLK_GPIO1_GATE&amp;gt;;
			clock-names = "gpio", "port";
			gpio-ranges = &amp;lt;&amp;amp;iomuxc 0 92 16&amp;gt;;
		};&lt;/LI-CODE&gt;</description>
      <pubDate>Sat, 08 Feb 2025 05:34:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Understanding-GPIO-Number-Calculation-for-GPIO2-IO00-on-IMX9352/m-p/2040322#M233762</guid>
      <dc:creator>xacov</dc:creator>
      <dc:date>2025-02-08T05:34:47Z</dc:date>
    </item>
    <item>
      <title>Re: Understanding GPIO Number Calculation for GPIO2_IO00 on IMX9352 Board</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Understanding-GPIO-Number-Calculation-for-GPIO2-IO00-on-IMX9352/m-p/2040350#M233765</link>
      <description>&lt;P&gt;LMAO&lt;/P&gt;</description>
      <pubDate>Sat, 08 Feb 2025 07:13:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Understanding-GPIO-Number-Calculation-for-GPIO2-IO00-on-IMX9352/m-p/2040350#M233765</guid>
      <dc:creator>gidame</dc:creator>
      <dc:date>2025-02-08T07:13:42Z</dc:date>
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