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    <title>i.MX Processors中的主题 Re: LPDDR Testing</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR-Testing/m-p/2033077#M233283</link>
    <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/203308"&gt;@JorgeCas&lt;/a&gt; ,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; I used the same &lt;STRONG&gt;LPDDR4 Configuration&lt;/STRONG&gt; w.r.t specific &lt;STRONG&gt;maaxboard osm93&lt;/STRONG&gt; board but still in the DDR Tool (v24.12). As I mentioned before, all three test scenarios are failed to pass. So, whether all turnaround cases are mandatory to pass ? Or What does the configuration do I need to follow for that to pass? Or By default, those test scenarios are are failed ? or Only &lt;EM&gt;Read-write compare&lt;/EM&gt;. &lt;EM&gt;Walking Zeros&lt;/EM&gt;, &lt;EM&gt;Walking Ones&lt;/EM&gt; works/get pass because in the User guide of the DDR Tool mentioned these three, so Please clarify the doubts.&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;Thanks &amp;amp; Regards&lt;BR /&gt;Ravikumar&lt;/P&gt;</description>
    <pubDate>Thu, 23 Jan 2025 09:29:17 GMT</pubDate>
    <dc:creator>Embedded-world</dc:creator>
    <dc:date>2025-01-23T09:29:17Z</dc:date>
    <item>
      <title>LPDDR Testing</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR-Testing/m-p/2032450#M233245</link>
      <description>&lt;P&gt;Dear Experts,&lt;/P&gt;&lt;P&gt;I am working with the Maaxboard OSM93 (Avnet) and testing the LPDDR scenarios. While testing the LPDDR, the &lt;STRONG&gt;operational test&lt;/STRONG&gt; results for the following scenarios have failed:&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;&lt;EM&gt;BIST - 1 write - 1 read turnaround&lt;/EM&gt;&lt;/LI&gt;&lt;LI&gt;&lt;EM&gt;BIST - 2 write - 2 read turnaround&lt;/EM&gt;&lt;/LI&gt;&lt;LI&gt;&lt;EM&gt;BIST - 4 write - 4 read turnaround&lt;/EM&gt;&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;How can I debug these scenarios? What configurations do I need to change? Please suggest the steps to pass all the test scenarios.&lt;BR /&gt;&lt;BR /&gt;Configuration:&lt;BR /&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Operational Testing" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/320892i4266803C41E0B511/image-size/large?v=v2&amp;amp;px=999" role="button" title="Screenshot 2025-01-22 204653.png" alt="Operational Testing" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;Operational Testing&lt;/span&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Device Configuration" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/320893i39D4B29627DD89EC/image-size/large?v=v2&amp;amp;px=999" role="button" title="Screenshot 2025-01-22 204707.png" alt="Device Configuration" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;Device Configuration&lt;/span&gt;&lt;/span&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thanks &amp;amp; Regards,&lt;/P&gt;&lt;P&gt;Ravikumar&lt;/P&gt;</description>
      <pubDate>Wed, 22 Jan 2025 15:24:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR-Testing/m-p/2032450#M233245</guid>
      <dc:creator>Embedded-world</dc:creator>
      <dc:date>2025-01-22T15:24:47Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR Testing</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR-Testing/m-p/2032543#M233256</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;Please try again selecting the exact i.MX part number and DDR technology, according to the board web page, it has a LPDDR4, and you are running the test for a LPDDR4X.&lt;/P&gt;
&lt;P&gt;Best regards.&lt;/P&gt;</description>
      <pubDate>Wed, 22 Jan 2025 18:12:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR-Testing/m-p/2032543#M233256</guid>
      <dc:creator>JorgeCas</dc:creator>
      <dc:date>2025-01-22T18:12:05Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR Testing</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR-Testing/m-p/2033077#M233283</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/203308"&gt;@JorgeCas&lt;/a&gt; ,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; I used the same &lt;STRONG&gt;LPDDR4 Configuration&lt;/STRONG&gt; w.r.t specific &lt;STRONG&gt;maaxboard osm93&lt;/STRONG&gt; board but still in the DDR Tool (v24.12). As I mentioned before, all three test scenarios are failed to pass. So, whether all turnaround cases are mandatory to pass ? Or What does the configuration do I need to follow for that to pass? Or By default, those test scenarios are are failed ? or Only &lt;EM&gt;Read-write compare&lt;/EM&gt;. &lt;EM&gt;Walking Zeros&lt;/EM&gt;, &lt;EM&gt;Walking Ones&lt;/EM&gt; works/get pass because in the User guide of the DDR Tool mentioned these three, so Please clarify the doubts.&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;Thanks &amp;amp; Regards&lt;BR /&gt;Ravikumar&lt;/P&gt;</description>
      <pubDate>Thu, 23 Jan 2025 09:29:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR-Testing/m-p/2033077#M233283</guid>
      <dc:creator>Embedded-world</dc:creator>
      <dc:date>2025-01-23T09:29:17Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR Testing</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR-Testing/m-p/2033298#M233307</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;Yes, it is mandatory to pass all the tests in DDR stress. It seems that it is not passing Write-Read-Compare test.&lt;/P&gt;
&lt;P&gt;Please check that you are entering the corresponding DDR features, PMIC and UART settings.&lt;/P&gt;
&lt;P&gt;Could you please share the board characteristics, .mex file and log?&lt;/P&gt;
&lt;P&gt;Best regards.&lt;/P&gt;</description>
      <pubDate>Thu, 23 Jan 2025 16:08:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR-Testing/m-p/2033298#M233307</guid>
      <dc:creator>JorgeCas</dc:creator>
      <dc:date>2025-01-23T16:08:28Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR Testing</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR-Testing/m-p/2033549#M233325</link>
      <description>Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/203308"&gt;@JorgeCas&lt;/a&gt;,&lt;BR /&gt;&lt;BR /&gt;As per the Avnet board, 100% the test is passing with Read - Write compare scenario.&lt;BR /&gt;&lt;BR /&gt;But it's not passing the all other turnaround test case.&lt;BR /&gt;&lt;BR /&gt;Thanks &amp;amp; Regards&lt;BR /&gt;Ravikumar</description>
      <pubDate>Fri, 24 Jan 2025 02:44:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR-Testing/m-p/2033549#M233325</guid>
      <dc:creator>Embedded-world</dc:creator>
      <dc:date>2025-01-24T02:44:24Z</dc:date>
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