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    <title>topic Re: IMX93 DDR Tool in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX93-DDR-Tool/m-p/2032611#M233259</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Thank you for your interest in NXP Semiconductor products,&lt;/P&gt;
&lt;P&gt;1. The Frequency Set-points are defined below and they aren't required to be updated.&lt;/P&gt;
&lt;P&gt;Number of FSP. This setting allows the user to select the number of frequency setpoints to include for the Hardware Fast Frequency Change.&lt;/P&gt;
&lt;P&gt;2. From your simulation (depending on the memory and the controller, as the transmission line characteristics, the optimum ODT will be determined.&lt;/P&gt;
&lt;P&gt;These are the desired ODT impedance in Ohm. Valid values for DDR4=240,120,80,60,40. Valid values for DDR3L=high-impedance,120,60,40. Valid values for LPDDR4=240,120,80,60,40.&lt;/P&gt;
&lt;P&gt;3. vTSA performs Virtual Timing Signal Analysis by running tests to determine margins of DDR subsystem.&lt;/P&gt;
&lt;P&gt;Diag Write Margin/ Diag Read Margin tests creates virtual data eye diagram for each DQ lanes.&lt;/P&gt;
&lt;P&gt;Regards&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Wed, 22 Jan 2025 21:55:00 GMT</pubDate>
    <dc:creator>JosephAtNXP</dc:creator>
    <dc:date>2025-01-22T21:55:00Z</dc:date>
    <item>
      <title>IMX93 DDR Tool</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX93-DDR-Tool/m-p/2032304#M233232</link>
      <description>&lt;P&gt;&lt;STRONG&gt;Dear Experts,&lt;/STRONG&gt;&lt;/P&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;In the latest version of the iMX DDR Tool v24.12, I am going to configure the 1GB and 2GB LPDDR4x memory for a custom board based on the iMX93. How should I choose the frequency set points (FSP)? Also, where can I find the DQ, ODT, and DS values for this configuration, or should I use the default values? Does it always depend on the memory? What is the significance of the vTSA test case in the DDT Tool?&lt;BR /&gt;&lt;BR /&gt;Frequency Set Points( FSP):&amp;nbsp;&lt;BR /&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Frequency set points (fsp)" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/320839iCF1C70D3D22BB153/image-size/large?v=v2&amp;amp;px=999" role="button" title="Screenshot 2025-01-22 161642.png" alt="Frequency set points (fsp)" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;Frequency set points (fsp)&lt;/span&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;DQ, ODT &amp;amp; DS configuration:&amp;nbsp;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DQ, ODT, DS Config" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/320838iEC5D8A6486232672/image-size/large?v=v2&amp;amp;px=999" role="button" title="Untitled.png" alt="DQ, ODT, DS Config" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;DQ, ODT, DS Config&lt;/span&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;Please clarify the above doubts with respect to the LPDDR4x memory configuration.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;Thanks &amp;amp; Regards,&lt;BR /&gt;Ravikumar&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Wed, 22 Jan 2025 11:05:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX93-DDR-Tool/m-p/2032304#M233232</guid>
      <dc:creator>Embedded-world</dc:creator>
      <dc:date>2025-01-22T11:05:26Z</dc:date>
    </item>
    <item>
      <title>Re: IMX93 DDR Tool</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX93-DDR-Tool/m-p/2032611#M233259</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Thank you for your interest in NXP Semiconductor products,&lt;/P&gt;
&lt;P&gt;1. The Frequency Set-points are defined below and they aren't required to be updated.&lt;/P&gt;
&lt;P&gt;Number of FSP. This setting allows the user to select the number of frequency setpoints to include for the Hardware Fast Frequency Change.&lt;/P&gt;
&lt;P&gt;2. From your simulation (depending on the memory and the controller, as the transmission line characteristics, the optimum ODT will be determined.&lt;/P&gt;
&lt;P&gt;These are the desired ODT impedance in Ohm. Valid values for DDR4=240,120,80,60,40. Valid values for DDR3L=high-impedance,120,60,40. Valid values for LPDDR4=240,120,80,60,40.&lt;/P&gt;
&lt;P&gt;3. vTSA performs Virtual Timing Signal Analysis by running tests to determine margins of DDR subsystem.&lt;/P&gt;
&lt;P&gt;Diag Write Margin/ Diag Read Margin tests creates virtual data eye diagram for each DQ lanes.&lt;/P&gt;
&lt;P&gt;Regards&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 22 Jan 2025 21:55:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX93-DDR-Tool/m-p/2032611#M233259</guid>
      <dc:creator>JosephAtNXP</dc:creator>
      <dc:date>2025-01-22T21:55:00Z</dc:date>
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